2 * (C) Copyright 2014-2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
6 * Extracted from armv8/start.S
10 #include <linux/linkage.h>
12 #include <asm/macro.h>
14 #include <asm/arch/mp.h>
16 #ifdef CONFIG_FSL_LSCH3
17 #include <asm/arch-fsl-layerscape/immap_lsch3.h>
21 mov x29, lr /* Save LR */
23 #ifdef CONFIG_FSL_LSCH3
25 /* Set Wuo bit for RN-I 20 */
27 ldr x0, =CCI_AUX_CONTROL_BASE(20)
32 /* Add fully-coherent masters to DVM domain */
34 ldr x1, =CCI_MN_RNF_NODEID_LIST
35 ldr x2, =CCI_MN_DVM_DOMAIN_CTL_SET
36 bl ccn504_add_masters_to_dvm
38 /* Set all RN-I ports to QoS of 15 */
39 ldr x0, =CCI_S0_QOS_CONTROL_BASE(0)
42 ldr x0, =CCI_S1_QOS_CONTROL_BASE(0)
45 ldr x0, =CCI_S2_QOS_CONTROL_BASE(0)
49 ldr x0, =CCI_S0_QOS_CONTROL_BASE(2)
52 ldr x0, =CCI_S1_QOS_CONTROL_BASE(2)
55 ldr x0, =CCI_S2_QOS_CONTROL_BASE(2)
59 ldr x0, =CCI_S0_QOS_CONTROL_BASE(6)
62 ldr x0, =CCI_S1_QOS_CONTROL_BASE(6)
65 ldr x0, =CCI_S2_QOS_CONTROL_BASE(6)
69 ldr x0, =CCI_S0_QOS_CONTROL_BASE(12)
72 ldr x0, =CCI_S1_QOS_CONTROL_BASE(12)
75 ldr x0, =CCI_S2_QOS_CONTROL_BASE(12)
79 ldr x0, =CCI_S0_QOS_CONTROL_BASE(16)
82 ldr x0, =CCI_S1_QOS_CONTROL_BASE(16)
85 ldr x0, =CCI_S2_QOS_CONTROL_BASE(16)
89 ldr x0, =CCI_S0_QOS_CONTROL_BASE(20)
92 ldr x0, =CCI_S1_QOS_CONTROL_BASE(20)
95 ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
101 /* Set the SMMU page size in the sACR register */
104 orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */
108 /* Initialize GIC Secure Bank Status */
109 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
110 branch_if_slave x0, 1f
116 bl gic_init_secure_percpu
117 #elif defined(CONFIG_GICV2)
120 bl gic_init_secure_percpu
124 branch_if_master x0, x1, 2f
126 #if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
127 ldr x0, =secondary_boot_func
132 #ifdef CONFIG_FSL_TZPC_BP147
133 /* Set Non Secure access for all devices protected via TZPC */
134 ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
135 orr w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */
142 #ifdef CONFIG_FSL_TZASC_400
143 /* Set TZASC so that:
144 * a. We use only Region0 whose global secure write/read is EN
145 * b. We use only Region0 whose NSAID write/read is EN
147 * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
150 ldr x1, =TZASC_GATE_KEEPER(0)
151 ldr w0, [x1] /* Filter 0 Gate Keeper Register */
152 orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
155 ldr x1, =TZASC_GATE_KEEPER(1)
156 ldr w0, [x1] /* Filter 0 Gate Keeper Register */
157 orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
160 ldr x1, =TZASC_REGION_ATTRIBUTES_0(0)
161 ldr w0, [x1] /* Region-0 Attributes Register */
162 orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
163 orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
166 ldr x1, =TZASC_REGION_ATTRIBUTES_0(1)
167 ldr w0, [x1] /* Region-1 Attributes Register */
168 orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
169 orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
172 ldr x1, =TZASC_REGION_ID_ACCESS_0(0)
173 ldr w0, [x1] /* Region-0 Access Register */
174 mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
177 ldr x1, =TZASC_REGION_ID_ACCESS_0(1)
178 ldr w0, [x1] /* Region-1 Attributes Register */
179 mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
186 #ifdef CONFIG_ARCH_LS1046A
187 /* Initialize the L2 RAM latency */
188 mrs x1, S3_1_c11_c0_2
190 /* Clear L2 Tag RAM latency and L2 Data RAM latency */
192 /* Set L2 data ram latency bits [2:0] */
194 /* set L2 tag ram latency bits [8:6] */
196 msr S3_1_c11_c0_2, x1
200 mov lr, x29 /* Restore LR */
202 ENDPROC(lowlevel_init)
204 #ifdef CONFIG_FSL_LSCH3
207 ldr x1, =FSL_LSCH3_SVR
212 /* x0 has the desired status, return 0 for success, 1 for timeout
213 * clobber x1, x2, x3, x4, x6, x7
216 mov x7, #0 /* flag for timeout */
217 mrs x3, cntpct_el0 /* read timer */
218 add x3, x3, #1200 /* timeout after 100 microseconds */
220 movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */
221 mov w6, #8 /* HN-F node count */
224 cmp x2, x1 /* check status */
229 mov x7, #1 /* timeout */
232 add x0, x0, #0x10000 /* move to next node */
240 /* x0 has the desired state, clobber x1, x2, x6 */
242 /* power state to SFONLY */
243 mov w6, #8 /* HN-F node count */
245 movk x0, #0x420, lsl #16 /* HNF0_PSTATE_REQ */
246 1: /* set pstate to sfonly */
248 and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */
251 add x0, x0, #0x10000 /* move to next node */
257 ENTRY(__asm_flush_l3_dcache)
259 * Return status in x0
261 * tmeout 1 for setting SFONLY, 2 for FAM, 3 for both
267 mov x0, #0x1 /* HNFPSTAT_SFONLY */
270 mov x0, #0x4 /* SFONLY status */
273 mov x8, #1 /* timeout */
276 mov x0, #0x3 /* HNFPSTAT_FAM */
279 mov x0, #0xc /* FAM status */
287 ENDPROC(__asm_flush_l3_dcache)
291 /* Keep literals not used by the secondary boot code outside it */
294 /* Using 64 bit alignment since the spin table is accessed as data */
296 .global secondary_boot_code
297 /* Secondary Boot Code starts here */
301 .space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
304 ENTRY(secondary_boot_func)
307 * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
308 * MPIDR[7:2] = AFF0_RES
309 * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
310 * MPIDR[23:16] = AFF2_CLUSTERID
312 * MPIDR[29:25] = RES0
315 * MPIDR[39:32] = AFF3
317 * Linear Processor ID (LPID) calculation from MPIDR_EL1:
318 * (We only use AFF0_CPUID and AFF1_CLUSTERID for now
319 * until AFF2_CLUSTERID and AFF3 have non-zero values)
321 * LPID = MPIDR[15:8] | MPIDR[1:0]
326 orr x10, x2, x1, lsl #2 /* x10 has LPID */
327 ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */
329 * offset of the spin table element for this core from start of spin
330 * table (each elem is padded to 64 bytes)
333 ldr x0, =__spin_table
334 /* physical address of this cpus spin table element */
337 ldr x0, =__real_cntfrq
339 msr cntfrq_el0, x0 /* set with real frequency */
340 str x9, [x11, #16] /* LPID */
342 str x4, [x11, #8] /* STATUS */
344 #if defined(CONFIG_GICV3)
345 gic_wait_for_interrupt_m x0
346 #elif defined(CONFIG_GICV2)
348 gic_wait_for_interrupt_m x0, w1
351 bl secondary_switch_to_el2
352 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
353 bl secondary_switch_to_el1
360 #ifndef CONFIG_ARMV8_SWITCH_TO_EL1
365 tbz x1, #25, cpu_is_le
366 rev x0, x0 /* BE to LE conversion */
368 br x0 /* branch to the given address */
369 ENDPROC(secondary_boot_func)
371 ENTRY(secondary_switch_to_el2)
372 switch_el x0, 1f, 0f, 0f
374 1: armv8_switch_to_el2_m x0
375 ENDPROC(secondary_switch_to_el2)
377 ENTRY(secondary_switch_to_el1)
378 switch_el x0, 0f, 1f, 0f
380 1: armv8_switch_to_el1_m x0, x1
381 ENDPROC(secondary_switch_to_el1)
383 /* Ensure that the literals used by the secondary boot code are
384 * assembled within it (this is required so that we can protect
385 * this area with a single memreserve region
389 /* 64 bit alignment for elements accessed as data */
391 .global __real_cntfrq
393 .quad COUNTER_FREQUENCY
394 .globl __secondary_boot_code_size
395 .type __secondary_boot_code_size, %object
396 /* Secondary Boot Code ends here */
397 __secondary_boot_code_size:
398 .quad .-secondary_boot_code