1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2014-2015 Freescale Semiconductor
5 * Extracted from armv8/start.S
9 #include <linux/linkage.h>
11 #include <asm/macro.h>
12 #include <asm/arch-fsl-layerscape/soc.h>
14 #include <asm/arch/mp.h>
16 #ifdef CONFIG_FSL_LSCH3
17 #include <asm/arch-fsl-layerscape/immap_lsch3.h>
19 #include <asm/u-boot.h>
22 * For LS1043a rev1.0, GIC base address align with 4k.
23 * For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
24 * is set, GIC base address align with 4K, or else align
27 * x0: the base address of GICD
28 * x1: the base address of GICC
35 #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
36 ldr x2, =DCFG_CCSR_SVR
40 ldr w4, =SVR_DEV(SVR_LS1043A)
46 ldr x2, =SCFG_GIC400_ALIGN
49 tbnz w2, #GIC_ADDR_BIT, 1f
50 ldr x0, =GICD_BASE_64K
52 ldr x1, =GICC_BASE_64K
57 ENDPROC(get_gic_offset)
59 ENTRY(smp_kick_all_cpus)
60 /* Kick secondary cpus up by SGI 0 interrupt */
61 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
62 mov x29, lr /* Save LR */
64 bl gic_kick_secondary_cpus
65 mov lr, x29 /* Restore LR */
68 ENDPROC(smp_kick_all_cpus)
72 mov x29, lr /* Save LR */
74 switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
77 #if defined (CONFIG_SYS_FSL_HAS_CCN504)
79 /* Set Wuo bit for RN-I 20 */
80 #ifdef CONFIG_ARCH_LS2080A
81 ldr x0, =CCI_AUX_CONTROL_BASE(20)
86 * Set forced-order mode in RNI-6, RNI-20
87 * This is required for performance optimization on LS2088A
88 * LS2080A family does not support setting forced-order mode,
89 * so skip this operation for LS2080A family
93 ldr w1, =SVR_DEV(SVR_LS2080A)
97 ldr x0, =CCI_AUX_CONTROL_BASE(6)
100 ldr x0, =CCI_AUX_CONTROL_BASE(20)
106 /* Add fully-coherent masters to DVM domain */
108 ldr x1, =CCI_MN_RNF_NODEID_LIST
109 ldr x2, =CCI_MN_DVM_DOMAIN_CTL_SET
110 bl ccn504_add_masters_to_dvm
112 /* Set all RN-I ports to QoS of 15 */
113 ldr x0, =CCI_S0_QOS_CONTROL_BASE(0)
116 ldr x0, =CCI_S1_QOS_CONTROL_BASE(0)
119 ldr x0, =CCI_S2_QOS_CONTROL_BASE(0)
123 ldr x0, =CCI_S0_QOS_CONTROL_BASE(2)
126 ldr x0, =CCI_S1_QOS_CONTROL_BASE(2)
129 ldr x0, =CCI_S2_QOS_CONTROL_BASE(2)
133 ldr x0, =CCI_S0_QOS_CONTROL_BASE(6)
136 ldr x0, =CCI_S1_QOS_CONTROL_BASE(6)
139 ldr x0, =CCI_S2_QOS_CONTROL_BASE(6)
143 ldr x0, =CCI_S0_QOS_CONTROL_BASE(12)
146 ldr x0, =CCI_S1_QOS_CONTROL_BASE(12)
149 ldr x0, =CCI_S2_QOS_CONTROL_BASE(12)
153 ldr x0, =CCI_S0_QOS_CONTROL_BASE(16)
156 ldr x0, =CCI_S1_QOS_CONTROL_BASE(16)
159 ldr x0, =CCI_S2_QOS_CONTROL_BASE(16)
163 ldr x0, =CCI_S0_QOS_CONTROL_BASE(20)
166 ldr x0, =CCI_S1_QOS_CONTROL_BASE(20)
169 ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
172 #endif /* CONFIG_SYS_FSL_HAS_CCN504 */
175 /* Set the SMMU page size in the sACR register */
178 orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */
182 /* Initialize GIC Secure Bank Status */
183 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
184 branch_if_slave x0, 1f
190 bl gic_init_secure_percpu
191 #elif defined(CONFIG_GICV2)
193 bl gic_init_secure_percpu
198 branch_if_master x0, x1, 2f
200 #if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
201 ldr x0, =secondary_boot_func
206 switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
208 #ifdef CONFIG_FSL_TZPC_BP147
209 /* Set Non Secure access for all devices protected via TZPC */
210 ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
211 orr w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */
218 #ifdef CONFIG_FSL_TZASC_400
220 * LS2080 and its personalities does not support TZASC
221 * So skip TZASC related operations
225 ldr w1, =SVR_DEV(SVR_LS2080A)
229 /* Set TZASC so that:
230 * a. We use only Region0 whose global secure write/read is EN
231 * b. We use only Region0 whose NSAID write/read is EN
233 * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
237 .macro tzasc_prog, xreg
246 ldr w0, [x1] /* Filter 0 Gate Keeper Register */
247 orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
253 ldr w0, [x1] /* Region-0 Attributes Register */
254 orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
255 orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
261 ldr w0, [x1] /* Region-0 Access Register */
262 mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
266 #ifdef CONFIG_FSL_TZASC_1
271 #ifdef CONFIG_FSL_TZASC_2
281 #ifdef CONFIG_ARCH_LS1046A
282 switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
284 /* Initialize the L2 RAM latency */
285 mrs x1, S3_1_c11_c0_2
287 /* Clear L2 Tag RAM latency and L2 Data RAM latency */
289 /* Set L2 data ram latency bits [2:0] */
291 /* set L2 tag ram latency bits [8:6] */
293 msr S3_1_c11_c0_2, x1
298 #if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
302 mov lr, x29 /* Restore LR */
304 ENDPROC(lowlevel_init)
306 #if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
307 ENTRY(fsl_ocram_init)
308 mov x28, lr /* Save LR */
310 bl fsl_ocram_clear_ecc_err
311 mov lr, x28 /* Restore LR */
313 ENDPROC(fsl_ocram_init)
315 ENTRY(fsl_clear_ocram)
317 ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE
318 ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
326 ENDPROC(fsl_clear_ocram)
328 ENTRY(fsl_ocram_clear_ecc_err)
329 /* OCRAM1/2 ECC status bit */
331 ldr x0, =DCSR_DCFG_SBEESR2
333 ldr x0, =DCSR_DCFG_MBEESR2
336 ENDPROC(fsl_ocram_init)
339 #ifdef CONFIG_FSL_LSCH3
342 ldr x1, =FSL_LSCH3_SVR
347 #ifdef CONFIG_SYS_FSL_HAS_CCN504
349 /* x0 has the desired status, return 0 for success, 1 for timeout
350 * clobber x1, x2, x3, x4, x6, x7
353 mov x7, #0 /* flag for timeout */
354 mrs x3, cntpct_el0 /* read timer */
355 add x3, x3, #1200 /* timeout after 100 microseconds */
357 movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */
358 mov w6, #8 /* HN-F node count */
361 cmp x2, x1 /* check status */
366 mov x7, #1 /* timeout */
369 add x0, x0, #0x10000 /* move to next node */
377 /* x0 has the desired state, clobber x1, x2, x6 */
379 /* power state to SFONLY */
380 mov w6, #8 /* HN-F node count */
382 movk x0, #0x420, lsl #16 /* HNF0_PSTATE_REQ */
383 1: /* set pstate to sfonly */
385 and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */
388 add x0, x0, #0x10000 /* move to next node */
394 ENTRY(__asm_flush_l3_dcache)
396 * Return status in x0
398 * timeout 1 for setting SFONLY, 2 for FAM, 3 for both
404 mov x0, #0x1 /* HNFPSTAT_SFONLY */
407 mov x0, #0x4 /* SFONLY status */
410 mov x8, #1 /* timeout */
413 mov x0, #0x3 /* HNFPSTAT_FAM */
416 mov x0, #0xc /* FAM status */
424 ENDPROC(__asm_flush_l3_dcache)
425 #endif /* CONFIG_SYS_FSL_HAS_CCN504 */
428 /* Keep literals not used by the secondary boot code outside it */
431 /* Using 64 bit alignment since the spin table is accessed as data */
433 .global secondary_boot_code
434 /* Secondary Boot Code starts here */
438 .space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
441 ENTRY(secondary_boot_func)
444 * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
445 * MPIDR[7:2] = AFF0_RES
446 * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
447 * MPIDR[23:16] = AFF2_CLUSTERID
449 * MPIDR[29:25] = RES0
452 * MPIDR[39:32] = AFF3
454 * Linear Processor ID (LPID) calculation from MPIDR_EL1:
455 * (We only use AFF0_CPUID and AFF1_CLUSTERID for now
456 * until AFF2_CLUSTERID and AFF3 have non-zero values)
458 * LPID = MPIDR[15:8] | MPIDR[1:0]
463 orr x10, x2, x1, lsl #2 /* x10 has LPID */
464 ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */
466 * offset of the spin table element for this core from start of spin
467 * table (each elem is padded to 64 bytes)
470 ldr x0, =__spin_table
471 /* physical address of this cpus spin table element */
474 ldr x0, =__real_cntfrq
476 msr cntfrq_el0, x0 /* set with real frequency */
477 str x9, [x11, #16] /* LPID */
479 str x4, [x11, #8] /* STATUS */
481 #if defined(CONFIG_GICV3)
482 gic_wait_for_interrupt_m x0
483 #elif defined(CONFIG_GICV2)
486 gic_wait_for_interrupt_m x0, w1
493 #ifndef CONFIG_ARMV8_SWITCH_TO_EL1
498 tbz x1, #25, cpu_is_le
499 rev x0, x0 /* BE to LE conversion */
504 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
505 adr x4, secondary_switch_to_el1
506 ldr x5, =ES_TO_AARCH64
509 ldr x5, =ES_TO_AARCH32
511 bl secondary_switch_to_el2
514 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
515 adr x4, secondary_switch_to_el1
519 ldr x5, =ES_TO_AARCH64
520 bl secondary_switch_to_el2
522 ENDPROC(secondary_boot_func)
524 ENTRY(secondary_switch_to_el2)
525 switch_el x6, 1f, 0f, 0f
527 1: armv8_switch_to_el2_m x4, x5, x6
528 ENDPROC(secondary_switch_to_el2)
530 ENTRY(secondary_switch_to_el1)
534 orr x10, x2, x1, lsl #2 /* x10 has LPID */
537 ldr x0, =__spin_table
538 /* physical address of this cpus spin table element */
546 ldr x5, =ES_TO_AARCH32
549 2: ldr x5, =ES_TO_AARCH64
552 switch_el x6, 0f, 1f, 0f
554 1: armv8_switch_to_el1_m x4, x5, x6
555 ENDPROC(secondary_switch_to_el1)
557 /* Ensure that the literals used by the secondary boot code are
558 * assembled within it (this is required so that we can protect
559 * this area with a single memreserve region
563 /* 64 bit alignment for elements accessed as data */
565 .global __real_cntfrq
567 .quad COUNTER_FREQUENCY
568 .globl __secondary_boot_code_size
569 .type __secondary_boot_code_size, %object
570 /* Secondary Boot Code ends here */
571 __secondary_boot_code_size:
572 .quad .-secondary_boot_code