2 * (C) Copyright 2014-2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
6 * Extracted from armv8/start.S
10 #include <linux/linkage.h>
12 #include <asm/macro.h>
13 #include <asm/arch-fsl-layerscape/soc.h>
15 #include <asm/arch/mp.h>
17 #ifdef CONFIG_FSL_LSCH3
18 #include <asm/arch-fsl-layerscape/immap_lsch3.h>
20 #include <asm/u-boot.h>
23 * For LS1043a rev1.0, GIC base address align with 4k.
24 * For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
25 * is set, GIC base address align with 4K, or else align
28 * x0: the base address of GICD
29 * x1: the base address of GICC
36 #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
37 ldr x2, =DCFG_CCSR_SVR
41 ldr w4, =SVR_DEV(SVR_LS1043A)
47 ldr x2, =SCFG_GIC400_ALIGN
50 tbnz w2, #GIC_ADDR_BIT, 1f
51 ldr x0, =GICD_BASE_64K
53 ldr x1, =GICC_BASE_64K
58 ENDPROC(get_gic_offset)
60 ENTRY(smp_kick_all_cpus)
61 /* Kick secondary cpus up by SGI 0 interrupt */
62 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
63 mov x29, lr /* Save LR */
65 bl gic_kick_secondary_cpus
66 mov lr, x29 /* Restore LR */
69 ENDPROC(smp_kick_all_cpus)
73 mov x29, lr /* Save LR */
75 switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
78 #if defined (CONFIG_SYS_FSL_HAS_CCN504)
80 /* Set Wuo bit for RN-I 20 */
81 #ifdef CONFIG_ARCH_LS2080A
82 ldr x0, =CCI_AUX_CONTROL_BASE(20)
87 * Set forced-order mode in RNI-6, RNI-20
88 * This is required for performance optimization on LS2088A
89 * LS2080A family does not support setting forced-order mode,
90 * so skip this operation for LS2080A family
94 ldr w1, =SVR_DEV(SVR_LS2080A)
98 ldr x0, =CCI_AUX_CONTROL_BASE(6)
101 ldr x0, =CCI_AUX_CONTROL_BASE(20)
107 /* Add fully-coherent masters to DVM domain */
109 ldr x1, =CCI_MN_RNF_NODEID_LIST
110 ldr x2, =CCI_MN_DVM_DOMAIN_CTL_SET
111 bl ccn504_add_masters_to_dvm
113 /* Set all RN-I ports to QoS of 15 */
114 ldr x0, =CCI_S0_QOS_CONTROL_BASE(0)
117 ldr x0, =CCI_S1_QOS_CONTROL_BASE(0)
120 ldr x0, =CCI_S2_QOS_CONTROL_BASE(0)
124 ldr x0, =CCI_S0_QOS_CONTROL_BASE(2)
127 ldr x0, =CCI_S1_QOS_CONTROL_BASE(2)
130 ldr x0, =CCI_S2_QOS_CONTROL_BASE(2)
134 ldr x0, =CCI_S0_QOS_CONTROL_BASE(6)
137 ldr x0, =CCI_S1_QOS_CONTROL_BASE(6)
140 ldr x0, =CCI_S2_QOS_CONTROL_BASE(6)
144 ldr x0, =CCI_S0_QOS_CONTROL_BASE(12)
147 ldr x0, =CCI_S1_QOS_CONTROL_BASE(12)
150 ldr x0, =CCI_S2_QOS_CONTROL_BASE(12)
154 ldr x0, =CCI_S0_QOS_CONTROL_BASE(16)
157 ldr x0, =CCI_S1_QOS_CONTROL_BASE(16)
160 ldr x0, =CCI_S2_QOS_CONTROL_BASE(16)
164 ldr x0, =CCI_S0_QOS_CONTROL_BASE(20)
167 ldr x0, =CCI_S1_QOS_CONTROL_BASE(20)
170 ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
173 #endif /* CONFIG_SYS_FSL_HAS_CCN504 */
176 /* Set the SMMU page size in the sACR register */
179 orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */
183 /* Initialize GIC Secure Bank Status */
184 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
185 branch_if_slave x0, 1f
191 bl gic_init_secure_percpu
192 #elif defined(CONFIG_GICV2)
194 bl gic_init_secure_percpu
199 branch_if_master x0, x1, 2f
201 #if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
202 ldr x0, =secondary_boot_func
207 switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
209 #ifdef CONFIG_FSL_TZPC_BP147
210 /* Set Non Secure access for all devices protected via TZPC */
211 ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
212 orr w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */
219 #ifdef CONFIG_FSL_TZASC_400
221 * LS2080 and its personalities does not support TZASC
222 * So skip TZASC related operations
226 ldr w1, =SVR_DEV(SVR_LS2080A)
230 /* Set TZASC so that:
231 * a. We use only Region0 whose global secure write/read is EN
232 * b. We use only Region0 whose NSAID write/read is EN
234 * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
237 #ifdef CONFIG_FSL_TZASC_1
238 ldr x1, =TZASC_GATE_KEEPER(0)
239 ldr w0, [x1] /* Filter 0 Gate Keeper Register */
240 orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
243 ldr x1, =TZASC_REGION_ATTRIBUTES_0(0)
244 ldr w0, [x1] /* Region-0 Attributes Register */
245 orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
246 orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
249 ldr x1, =TZASC_REGION_ID_ACCESS_0(0)
250 ldr w0, [x1] /* Region-0 Access Register */
251 mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
254 #ifdef CONFIG_FSL_TZASC_2
255 ldr x1, =TZASC_GATE_KEEPER(1)
256 ldr w0, [x1] /* Filter 0 Gate Keeper Register */
257 orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
260 ldr x1, =TZASC_REGION_ATTRIBUTES_0(1)
261 ldr w0, [x1] /* Region-1 Attributes Register */
262 orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
263 orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
266 ldr x1, =TZASC_REGION_ID_ACCESS_0(1)
267 ldr w0, [x1] /* Region-1 Attributes Register */
268 mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
276 #ifdef CONFIG_ARCH_LS1046A
277 switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
279 /* Initialize the L2 RAM latency */
280 mrs x1, S3_1_c11_c0_2
282 /* Clear L2 Tag RAM latency and L2 Data RAM latency */
284 /* Set L2 data ram latency bits [2:0] */
286 /* set L2 tag ram latency bits [8:6] */
288 msr S3_1_c11_c0_2, x1
293 #if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
297 mov lr, x29 /* Restore LR */
299 ENDPROC(lowlevel_init)
301 #if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
302 ENTRY(fsl_ocram_init)
303 mov x28, lr /* Save LR */
305 bl fsl_ocram_clear_ecc_err
306 mov lr, x28 /* Restore LR */
308 ENDPROC(fsl_ocram_init)
310 ENTRY(fsl_clear_ocram)
312 ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE
313 ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
321 ENDPROC(fsl_clear_ocram)
323 ENTRY(fsl_ocram_clear_ecc_err)
324 /* OCRAM1/2 ECC status bit */
326 ldr x0, =DCSR_DCFG_SBEESR2
328 ldr x0, =DCSR_DCFG_MBEESR2
331 ENDPROC(fsl_ocram_init)
334 #ifdef CONFIG_FSL_LSCH3
337 ldr x1, =FSL_LSCH3_SVR
342 #ifdef CONFIG_SYS_FSL_HAS_CCN504
344 /* x0 has the desired status, return 0 for success, 1 for timeout
345 * clobber x1, x2, x3, x4, x6, x7
348 mov x7, #0 /* flag for timeout */
349 mrs x3, cntpct_el0 /* read timer */
350 add x3, x3, #1200 /* timeout after 100 microseconds */
352 movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */
353 mov w6, #8 /* HN-F node count */
356 cmp x2, x1 /* check status */
361 mov x7, #1 /* timeout */
364 add x0, x0, #0x10000 /* move to next node */
372 /* x0 has the desired state, clobber x1, x2, x6 */
374 /* power state to SFONLY */
375 mov w6, #8 /* HN-F node count */
377 movk x0, #0x420, lsl #16 /* HNF0_PSTATE_REQ */
378 1: /* set pstate to sfonly */
380 and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */
383 add x0, x0, #0x10000 /* move to next node */
389 ENTRY(__asm_flush_l3_dcache)
391 * Return status in x0
393 * timeout 1 for setting SFONLY, 2 for FAM, 3 for both
399 mov x0, #0x1 /* HNFPSTAT_SFONLY */
402 mov x0, #0x4 /* SFONLY status */
405 mov x8, #1 /* timeout */
408 mov x0, #0x3 /* HNFPSTAT_FAM */
411 mov x0, #0xc /* FAM status */
419 ENDPROC(__asm_flush_l3_dcache)
420 #endif /* CONFIG_SYS_FSL_HAS_CCN504 */
423 /* Keep literals not used by the secondary boot code outside it */
426 /* Using 64 bit alignment since the spin table is accessed as data */
428 .global secondary_boot_code
429 /* Secondary Boot Code starts here */
433 .space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
436 ENTRY(secondary_boot_func)
439 * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
440 * MPIDR[7:2] = AFF0_RES
441 * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
442 * MPIDR[23:16] = AFF2_CLUSTERID
444 * MPIDR[29:25] = RES0
447 * MPIDR[39:32] = AFF3
449 * Linear Processor ID (LPID) calculation from MPIDR_EL1:
450 * (We only use AFF0_CPUID and AFF1_CLUSTERID for now
451 * until AFF2_CLUSTERID and AFF3 have non-zero values)
453 * LPID = MPIDR[15:8] | MPIDR[1:0]
458 orr x10, x2, x1, lsl #2 /* x10 has LPID */
459 ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */
461 * offset of the spin table element for this core from start of spin
462 * table (each elem is padded to 64 bytes)
465 ldr x0, =__spin_table
466 /* physical address of this cpus spin table element */
469 ldr x0, =__real_cntfrq
471 msr cntfrq_el0, x0 /* set with real frequency */
472 str x9, [x11, #16] /* LPID */
474 str x4, [x11, #8] /* STATUS */
476 #if defined(CONFIG_GICV3)
477 gic_wait_for_interrupt_m x0
478 #elif defined(CONFIG_GICV2)
481 gic_wait_for_interrupt_m x0, w1
488 #ifndef CONFIG_ARMV8_SWITCH_TO_EL1
493 tbz x1, #25, cpu_is_le
494 rev x0, x0 /* BE to LE conversion */
499 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
500 adr x4, secondary_switch_to_el1
501 ldr x5, =ES_TO_AARCH64
504 ldr x5, =ES_TO_AARCH32
506 bl secondary_switch_to_el2
509 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
510 adr x4, secondary_switch_to_el1
514 ldr x5, =ES_TO_AARCH64
515 bl secondary_switch_to_el2
517 ENDPROC(secondary_boot_func)
519 ENTRY(secondary_switch_to_el2)
520 switch_el x6, 1f, 0f, 0f
522 1: armv8_switch_to_el2_m x4, x5, x6
523 ENDPROC(secondary_switch_to_el2)
525 ENTRY(secondary_switch_to_el1)
529 orr x10, x2, x1, lsl #2 /* x10 has LPID */
532 ldr x0, =__spin_table
533 /* physical address of this cpus spin table element */
541 ldr x5, =ES_TO_AARCH32
544 2: ldr x5, =ES_TO_AARCH64
547 switch_el x6, 0f, 1f, 0f
549 1: armv8_switch_to_el1_m x4, x5, x6
550 ENDPROC(secondary_switch_to_el1)
552 /* Ensure that the literals used by the secondary boot code are
553 * assembled within it (this is required so that we can protect
554 * this area with a single memreserve region
558 /* 64 bit alignment for elements accessed as data */
560 .global __real_cntfrq
562 .quad COUNTER_FREQUENCY
563 .globl __secondary_boot_code_size
564 .type __secondary_boot_code_size, %object
565 /* Secondary Boot Code ends here */
566 __secondary_boot_code_size:
567 .quad .-secondary_boot_code