1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2014-2015 Freescale Semiconductor
6 * Extracted from armv8/start.S
10 #include <linux/linkage.h>
12 #include <asm/macro.h>
13 #include <asm/arch-fsl-layerscape/soc.h>
15 #include <asm/arch/mp.h>
17 #ifdef CONFIG_FSL_LSCH3
18 #include <asm/arch-fsl-layerscape/immap_lsch3.h>
20 #include <asm/u-boot.h>
23 * For LS1043a rev1.0, GIC base address align with 4k.
24 * For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
25 * is set, GIC base address align with 4K, or else align
28 * x0: the base address of GICD
29 * x1: the base address of GICC
36 #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
37 ldr x2, =DCFG_CCSR_SVR
41 ldr w4, =SVR_DEV(SVR_LS1043A)
47 ldr x2, =SCFG_GIC400_ALIGN
50 tbnz w2, #GIC_ADDR_BIT, 1f
51 ldr x0, =GICD_BASE_64K
53 ldr x1, =GICC_BASE_64K
58 ENDPROC(get_gic_offset)
60 ENTRY(smp_kick_all_cpus)
61 /* Kick secondary cpus up by SGI 0 interrupt */
62 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
63 mov x29, lr /* Save LR */
65 bl gic_kick_secondary_cpus
66 mov lr, x29 /* Restore LR */
69 ENDPROC(smp_kick_all_cpus)
73 mov x29, lr /* Save LR */
75 /* unmask SError and abort */
78 /* Set HCR_EL2[AMO] so SError @EL2 is taken */
80 orr x0, x0, #0x20 /* AMO */
84 switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
87 #if defined (CONFIG_SYS_FSL_HAS_CCN504)
89 /* Set Wuo bit for RN-I 20 */
90 #ifdef CONFIG_ARCH_LS2080A
91 ldr x0, =CCI_AUX_CONTROL_BASE(20)
96 * Set forced-order mode in RNI-6, RNI-20
97 * This is required for performance optimization on LS2088A
98 * LS2080A family does not support setting forced-order mode,
99 * so skip this operation for LS2080A family
103 ldr w1, =SVR_DEV(SVR_LS2080A)
107 ldr x0, =CCI_AUX_CONTROL_BASE(6)
110 ldr x0, =CCI_AUX_CONTROL_BASE(20)
116 /* Add fully-coherent masters to DVM domain */
118 ldr x1, =CCI_MN_RNF_NODEID_LIST
119 ldr x2, =CCI_MN_DVM_DOMAIN_CTL_SET
120 bl ccn504_add_masters_to_dvm
122 /* Set all RN-I ports to QoS of 15 */
123 ldr x0, =CCI_S0_QOS_CONTROL_BASE(0)
126 ldr x0, =CCI_S1_QOS_CONTROL_BASE(0)
129 ldr x0, =CCI_S2_QOS_CONTROL_BASE(0)
133 ldr x0, =CCI_S0_QOS_CONTROL_BASE(2)
136 ldr x0, =CCI_S1_QOS_CONTROL_BASE(2)
139 ldr x0, =CCI_S2_QOS_CONTROL_BASE(2)
143 ldr x0, =CCI_S0_QOS_CONTROL_BASE(6)
146 ldr x0, =CCI_S1_QOS_CONTROL_BASE(6)
149 ldr x0, =CCI_S2_QOS_CONTROL_BASE(6)
153 ldr x0, =CCI_S0_QOS_CONTROL_BASE(12)
156 ldr x0, =CCI_S1_QOS_CONTROL_BASE(12)
159 ldr x0, =CCI_S2_QOS_CONTROL_BASE(12)
163 ldr x0, =CCI_S0_QOS_CONTROL_BASE(16)
166 ldr x0, =CCI_S1_QOS_CONTROL_BASE(16)
169 ldr x0, =CCI_S2_QOS_CONTROL_BASE(16)
173 ldr x0, =CCI_S0_QOS_CONTROL_BASE(20)
176 ldr x0, =CCI_S1_QOS_CONTROL_BASE(20)
179 ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
182 #endif /* CONFIG_SYS_FSL_HAS_CCN504 */
185 /* Set the SMMU page size in the sACR register */
188 orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */
192 /* Initialize GIC Secure Bank Status */
193 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
194 branch_if_slave x0, 1f
200 bl gic_init_secure_percpu
201 #elif defined(CONFIG_GICV2)
203 bl gic_init_secure_percpu
208 branch_if_master x0, x1, 2f
210 #if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
211 ldr x0, =secondary_boot_func
216 switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
218 #ifdef CONFIG_FSL_TZPC_BP147
219 /* Set Non Secure access for all devices protected via TZPC */
220 ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
221 orr w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */
228 #ifdef CONFIG_FSL_TZASC_400
230 * LS2080 and its personalities does not support TZASC
231 * So skip TZASC related operations
235 ldr w1, =SVR_DEV(SVR_LS2080A)
239 /* Set TZASC so that:
240 * a. We use only Region0 whose global secure write/read is EN
241 * b. We use only Region0 whose NSAID write/read is EN
243 * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
247 .macro tzasc_prog, xreg
256 ldr w0, [x1] /* Filter 0 Gate Keeper Register */
257 orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
263 ldr w0, [x1] /* Region-0 Attributes Register */
264 orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
265 orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
271 ldr w0, [x1] /* Region-0 Access Register */
272 mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
276 #ifdef CONFIG_FSL_TZASC_1
281 #ifdef CONFIG_FSL_TZASC_2
291 #ifdef CONFIG_ARCH_LS1046A
292 switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
294 /* Initialize the L2 RAM latency */
295 mrs x1, S3_1_c11_c0_2
297 /* Clear L2 Tag RAM latency and L2 Data RAM latency */
299 /* Set L2 data ram latency bits [2:0] */
301 /* set L2 tag ram latency bits [8:6] */
303 msr S3_1_c11_c0_2, x1
308 #if !defined(CONFIG_TFABOOT) && \
309 (defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD))
313 mov lr, x29 /* Restore LR */
315 ENDPROC(lowlevel_init)
317 #if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
318 ENTRY(fsl_ocram_init)
319 mov x28, lr /* Save LR */
321 bl fsl_ocram_clear_ecc_err
322 mov lr, x28 /* Restore LR */
324 ENDPROC(fsl_ocram_init)
326 ENTRY(fsl_clear_ocram)
328 ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE
329 ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
337 ENDPROC(fsl_clear_ocram)
339 ENTRY(fsl_ocram_clear_ecc_err)
340 /* OCRAM1/2 ECC status bit */
342 ldr x0, =DCSR_DCFG_SBEESR2
344 ldr x0, =DCSR_DCFG_MBEESR2
347 ENDPROC(fsl_ocram_init)
350 #ifdef CONFIG_FSL_LSCH3
353 ldr x1, =FSL_LSCH3_SVR
358 #if defined(CONFIG_SYS_FSL_HAS_CCN504) || defined(CONFIG_SYS_FSL_HAS_CCN508)
360 /* x0 has the desired status, return only if operation succeed
364 mov w6, #8 /* HN-F node count */
366 movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */
369 cmp x2, x1 /* check status */
373 add x0, x0, #0x10000 /* move to next node */
379 /* x0 has the desired state, clobber x1, x2, x6 */
381 /* power state to SFONLY */
382 mov w6, #8 /* HN-F node count */
384 movk x0, #0x420, lsl #16 /* HNF0_PSTATE_REQ */
385 1: /* set pstate to sfonly */
387 and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */
390 add x0, x0, #0x10000 /* move to next node */
396 ENTRY(__asm_flush_l3_dcache)
398 * Return status in x0
404 mov x0, #0x1 /* HNFPSTAT_SFONLY */
407 mov x0, #0x4 /* SFONLY status */
411 mov x0, #0x3 /* HNFPSTAT_FAM */
414 mov x0, #0xc /* FAM status */
420 ENDPROC(__asm_flush_l3_dcache)
421 #endif /* CONFIG_SYS_FSL_HAS_CCN504 */
424 /* Keep literals not used by the secondary boot code outside it */
427 /* Using 64 bit alignment since the spin table is accessed as data */
429 .global secondary_boot_code
430 /* Secondary Boot Code starts here */
434 .space CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE
437 ENTRY(secondary_boot_func)
440 * MPIDR[1:0] = AFF0_CPUID <- Core ID (0,1)
441 * MPIDR[7:2] = AFF0_RES
442 * MPIDR[15:8] = AFF1_CLUSTERID <- Cluster ID (0,1,2,3)
443 * MPIDR[23:16] = AFF2_CLUSTERID
445 * MPIDR[29:25] = RES0
448 * MPIDR[39:32] = AFF3
450 * Linear Processor ID (LPID) calculation from MPIDR_EL1:
451 * (We only use AFF0_CPUID and AFF1_CLUSTERID for now
452 * until AFF2_CLUSTERID and AFF3 have non-zero values)
454 * LPID = MPIDR[15:8] | MPIDR[1:0]
459 orr x10, x2, x1, lsl #2 /* x10 has LPID */
460 ubfm x9, x0, #0, #15 /* x9 contains MPIDR[15:0] */
462 * offset of the spin table element for this core from start of spin
463 * table (each elem is padded to 64 bytes)
466 ldr x0, =__spin_table
467 /* physical address of this cpus spin table element */
470 ldr x0, =__real_cntfrq
472 msr cntfrq_el0, x0 /* set with real frequency */
473 str x9, [x11, #16] /* LPID */
475 str x4, [x11, #8] /* STATUS */
477 #if defined(CONFIG_GICV3)
478 gic_wait_for_interrupt_m x0
479 #elif defined(CONFIG_GICV2)
482 gic_wait_for_interrupt_m x0, w1
489 #ifndef CONFIG_ARMV8_SWITCH_TO_EL1
494 tbz x1, #25, cpu_is_le
495 rev x0, x0 /* BE to LE conversion */
500 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
501 adr x4, secondary_switch_to_el1
502 ldr x5, =ES_TO_AARCH64
505 ldr x5, =ES_TO_AARCH32
507 bl secondary_switch_to_el2
510 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
511 adr x4, secondary_switch_to_el1
515 ldr x5, =ES_TO_AARCH64
516 bl secondary_switch_to_el2
518 ENDPROC(secondary_boot_func)
520 ENTRY(secondary_switch_to_el2)
521 switch_el x6, 1f, 0f, 0f
523 1: armv8_switch_to_el2_m x4, x5, x6
524 ENDPROC(secondary_switch_to_el2)
526 ENTRY(secondary_switch_to_el1)
530 orr x10, x2, x1, lsl #2 /* x10 has LPID */
533 ldr x0, =__spin_table
534 /* physical address of this cpus spin table element */
542 ldr x5, =ES_TO_AARCH32
545 2: ldr x5, =ES_TO_AARCH64
548 switch_el x6, 0f, 1f, 0f
550 1: armv8_switch_to_el1_m x4, x5, x6
551 ENDPROC(secondary_switch_to_el1)
553 /* Ensure that the literals used by the secondary boot code are
554 * assembled within it (this is required so that we can protect
555 * this area with a single memreserve region
559 /* 64 bit alignment for elements accessed as data */
561 .global __real_cntfrq
563 .quad COUNTER_FREQUENCY
564 .globl __secondary_boot_code_size
565 .type __secondary_boot_code_size, %object
566 /* Secondary Boot Code ends here */
567 __secondary_boot_code_size:
568 .quad .-secondary_boot_code