1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Freescale Semiconductor, Inc.
8 #include <linux/compiler.h>
10 #include <asm/processor.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/soc.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
19 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
22 void get_sys_info(struct sys_info *sys_info)
24 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
25 /* rcw_tmp is needed to get FMAN clock, or to get cluster group A
26 * mux 2 clock for LS1043A/LS1046A.
28 #if defined(CONFIG_SYS_DPAA_FMAN) || \
29 defined(CONFIG_TARGET_LS1046ARDB) || \
30 defined(CONFIG_TARGET_LS1043ARDB)
33 struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
35 const u8 core_cplx_pll[8] = {
36 [0] = 0, /* CC1 PPL / 1 */
37 [1] = 0, /* CC1 PPL / 2 */
38 [4] = 1, /* CC2 PPL / 1 */
39 [5] = 1, /* CC2 PPL / 2 */
42 const u8 core_cplx_pll_div[8] = {
43 [0] = 1, /* CC1 PPL / 1 */
44 [1] = 2, /* CC1 PPL / 2 */
45 [4] = 1, /* CC2 PPL / 1 */
46 [5] = 2, /* CC2 PPL / 2 */
50 uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
51 uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
52 unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
53 unsigned long cluster_clk;
55 sys_info->freq_systembus = sysclk;
56 #ifndef CONFIG_CLUSTER_CLK_FREQ
57 #define CONFIG_CLUSTER_CLK_FREQ CONFIG_SYS_CLK_FREQ
59 cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
61 #ifdef CONFIG_DDR_CLK_FREQ
62 sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
64 sys_info->freq_ddrbus = sysclk;
67 /* The freq_systembus is used to record frequency of platform PLL */
68 sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
69 FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
70 FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
72 #ifdef CONFIG_ARCH_LS1012A
73 sys_info->freq_ddrbus = 2 * sys_info->freq_systembus;
75 sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
76 FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
77 FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
80 for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
81 ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
83 freq_c_pll[i] = cluster_clk * ratio[i];
85 freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
88 for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
89 cluster = fsl_qoriq_core_to_cluster(cpu);
90 u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
92 u32 cplx_pll = core_cplx_pll[c_pll_sel];
94 sys_info->freq_processor[cpu] =
95 freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
98 #define HWA_CGA_M1_CLK_SEL 0xe0000000
99 #define HWA_CGA_M1_CLK_SHIFT 29
100 #ifdef CONFIG_SYS_DPAA_FMAN
101 rcw_tmp = in_be32(&gur->rcwsr[7]);
102 switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
104 sys_info->freq_fman[0] = freq_c_pll[0] / 2;
107 sys_info->freq_fman[0] = freq_c_pll[0] / 3;
110 sys_info->freq_fman[0] = freq_c_pll[0] / 4;
113 sys_info->freq_fman[0] = sys_info->freq_systembus;
116 sys_info->freq_fman[0] = freq_c_pll[1] / 2;
119 sys_info->freq_fman[0] = freq_c_pll[1] / 3;
122 printf("Error: Unknown FMan1 clock select!\n");
127 #ifdef CONFIG_FSL_ESDHC
128 #define HWA_CGA_M2_CLK_SEL 0x00000007
129 #define HWA_CGA_M2_CLK_SHIFT 0
130 #if defined(CONFIG_TARGET_LS1046ARDB) || defined(CONFIG_TARGET_LS1043ARDB)
131 rcw_tmp = in_be32(&gur->rcwsr[15]);
132 switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
134 sys_info->freq_cga_m2 = freq_c_pll[1];
136 #if defined(CONFIG_TARGET_LS1046ARDB)
138 sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
142 sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
144 #if defined(CONFIG_TARGET_LS1046ARDB)
146 sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
150 printf("Error: Unknown peripheral clock select!\n");
156 #if defined(CONFIG_FSL_IFC)
157 sys_info->freq_localbus = sys_info->freq_systembus /
158 CONFIG_SYS_FSL_IFC_CLK_DIV;
160 #ifdef CONFIG_SYS_DPAA_QBMAN
161 sys_info->freq_qman = (sys_info->freq_systembus /
162 CONFIG_SYS_FSL_PCLK_DIV) /
163 CONFIG_SYS_FSL_QMAN_CLK_DIV;
167 #ifdef CONFIG_SYS_DPAA_QBMAN
168 unsigned long get_qman_freq(void)
170 struct sys_info sys_info;
172 get_sys_info(&sys_info);
174 return sys_info.freq_qman;
180 struct sys_info sys_info;
182 get_sys_info(&sys_info);
183 gd->cpu_clk = sys_info.freq_processor[0];
184 gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
185 gd->mem_clk = sys_info.freq_ddrbus;
187 #ifdef CONFIG_FSL_ESDHC
188 #if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
189 #if defined(CONFIG_TARGET_LS1046ARDB)
190 gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2;
192 #if defined(CONFIG_TARGET_LS1043ARDB)
193 gd->arch.sdhc_clk = sys_info.freq_cga_m2;
195 #if defined(CONFIG_TARGET_LS1012ARDB)
196 gd->arch.sdhc_clk = sys_info.freq_systembus;
199 gd->arch.sdhc_clk = (sys_info.freq_systembus /
200 CONFIG_SYS_FSL_PCLK_DIV) /
201 CONFIG_SYS_FSL_SDHC_CLK_DIV;
204 if (gd->cpu_clk != 0)
210 /********************************************
212 * return platform clock in Hz
213 *********************************************/
214 ulong get_bus_freq(ulong dummy)
222 ulong get_ddr_freq(ulong dummy)
230 #ifdef CONFIG_FSL_ESDHC
231 int get_sdhc_freq(ulong dummy)
233 if (!gd->arch.sdhc_clk)
236 return gd->arch.sdhc_clk;
240 int get_serial_clock(void)
242 return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
245 int get_i2c_freq(ulong dummy)
247 return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV;
250 int get_dspi_freq(ulong dummy)
252 return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
255 #ifdef CONFIG_FSL_LPUART
256 int get_uart_freq(ulong dummy)
258 return get_bus_freq(0) / CONFIG_SYS_FSL_LPUART_CLK_DIV;
262 unsigned int mxc_get_clock(enum mxc_clock clk)
266 return get_i2c_freq(0);
267 #if defined(CONFIG_FSL_ESDHC)
270 return get_sdhc_freq(0);
273 return get_dspi_freq(0);
274 #ifdef CONFIG_FSL_LPUART
276 return get_uart_freq(0);
279 printf("Unsupported clock\n");