4 # SPDX-License-Identifier: GPL-2.0+
7 NXP LayerScape with Chassis Generation 3.2
9 This architecture supports NXP ARMv8 SoCs with Chassis generation 3.2
12 This architecture is enhancement over Chassis Generation 3 with
13 few differences mentioned below
17 Entire DDR region splits into three regions.
18 - Region 1 is at address 0x8000_0000 to 0xffff_ffff.
19 - Region 2 is at address 0x20_8000_0000 to 0x3f_ffff_ffff,
20 - Region 3 is at address 0x60_0000_0000 to the top of memory,
21 for example 140GB, 0x63_7fff_ffff.
23 All DDR memory is marked as cache-enabled.
27 3)Number of I2C controllers increased to 8