arch/arm/cpu/armv8/fsl-layerscape/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2019 NXP
   4  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <env.h>
  10 #include <fsl_ddr_sdram.h>
  11 #include <vsprintf.h>
  12 #include <asm/io.h>
  13 #include <linux/errno.h>
  14 #include <asm/system.h>
  15 #include <fm_eth.h>
  16 #include <asm/armv8/mmu.h>
  17 #include <asm/io.h>
  18 #include <asm/arch/fsl_serdes.h>
  19 #include <asm/arch/soc.h>
  20 #include <asm/arch/cpu.h>
  21 #include <asm/arch/speed.h>
  22 #include <fsl_immap.h>
  23 #include <asm/arch/mp.h>
  24 #include <efi_loader.h>
  25 #include <fsl-mc/fsl_mc.h>
  26 #ifdef CONFIG_FSL_ESDHC
  27 #include <fsl_esdhc.h>
  28 #endif
  29 #include <asm/armv8/sec_firmware.h>
  30 #ifdef CONFIG_SYS_FSL_DDR
  31 #include <fsl_ddr.h>
  32 #endif
  33 #include <asm/arch/clock.h>
  34 #include <hwconfig.h>
  35 #include <fsl_qbman.h>
  36
  37 #ifdef CONFIG_TFABOOT
  38 #include <env_internal.h>
  39 #ifdef CONFIG_CHAIN_OF_TRUST
  40 #include <fsl_validate.h>
  41 #endif
  42 #endif
  43 #include <linux/mii.h>
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47 static struct cpu_type cpu_type_list[] = {
  48         CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
  49         CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
  50         CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
  51         CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
  52         CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
  53         CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
  54         CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
  55         CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
  56         CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
  57         CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
  58         CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
  59         CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
  60         CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
  61         CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
  62         CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
  63         CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
  64         CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
  65         CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
  66         CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
  67         CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
  68         CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
  69         CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
  70         CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
  71         CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
  72         CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
  73         CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
  74         CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
  75         CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
  76 };
  77
  78 #define EARLY_PGTABLE_SIZE 0x5000
  79 static struct mm_region early_map[] = {
  80 #ifdef CONFIG_FSL_LSCH3
  81         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
  82           CONFIG_SYS_FSL_CCSR_SIZE,
  83           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  84           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  85         },
  86         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  87           SYS_FSL_OCRAM_SPACE_SIZE,
  88           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
  89         },
  90         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
  91           CONFIG_SYS_FSL_QSPI_SIZE1,
  92           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
  93 #ifdef CONFIG_FSL_IFC
  94         /* For IFC Region #1, only the first 4MB is cache-enabled */
  95         { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
  96           CONFIG_SYS_FSL_IFC_SIZE1_1,
  97           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
  98         },
  99         { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
 100           CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
 101           CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
 102           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 103         },
 104         { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
 105           CONFIG_SYS_FSL_IFC_SIZE1,
 106           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 107         },
 108 #endif
 109         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 110           CONFIG_SYS_FSL_DRAM_SIZE1,
 111 #if defined(CONFIG_TFABOOT) || \
 112         (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 113           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 114 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
 115           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 116 #endif
 117           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 118         },
 119 #ifdef CONFIG_FSL_IFC
 120         /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
 121         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 122           CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
 123           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 124         },
 125 #endif
 126         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 127           CONFIG_SYS_FSL_DCSR_SIZE,
 128           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 129           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 130         },
 131         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 132           CONFIG_SYS_FSL_DRAM_SIZE2,
 133           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 134           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 135         },
 136 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 137         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 138           CONFIG_SYS_FSL_DRAM_SIZE3,
 139           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 140           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 141         },
 142 #endif
 143 #elif defined(CONFIG_FSL_LSCH2)
 144         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 145           CONFIG_SYS_FSL_CCSR_SIZE,
 146           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 147           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 148         },
 149         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 150           SYS_FSL_OCRAM_SPACE_SIZE,
 151           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 152         },
 153         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 154           CONFIG_SYS_FSL_DCSR_SIZE,
 155           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 156           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 157         },
 158         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 159           CONFIG_SYS_FSL_QSPI_SIZE,
 160           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 161         },
 162 #ifdef CONFIG_FSL_IFC
 163         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 164           CONFIG_SYS_FSL_IFC_SIZE,
 165           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 166         },
 167 #endif
 168         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 169           CONFIG_SYS_FSL_DRAM_SIZE1,
 170 #if defined(CONFIG_TFABOOT) || \
 171         (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 172           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 173 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
 174           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 175 #endif
 176           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 177         },
 178         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 179           CONFIG_SYS_FSL_DRAM_SIZE2,
 180           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 181           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 182         },
 183 #endif
 184         {},     /* list terminator */
 185 };
 186
 187 static struct mm_region final_map[] = {
 188 #ifdef CONFIG_FSL_LSCH3
 189         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 190           CONFIG_SYS_FSL_CCSR_SIZE,
 191           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 192           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 193         },
 194         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 195           SYS_FSL_OCRAM_SPACE_SIZE,
 196           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 197         },
 198         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 199           CONFIG_SYS_FSL_DRAM_SIZE1,
 200           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 201           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 202         },
 203         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
 204           CONFIG_SYS_FSL_QSPI_SIZE1,
 205           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 206           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 207         },
 208         { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
 209           CONFIG_SYS_FSL_QSPI_SIZE2,
 210           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 211           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 212         },
 213 #ifdef CONFIG_FSL_IFC
 214         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 215           CONFIG_SYS_FSL_IFC_SIZE2,
 216           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 217           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 218         },
 219 #endif
 220         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 221           CONFIG_SYS_FSL_DCSR_SIZE,
 222           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 223           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 224         },
 225         { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
 226           CONFIG_SYS_FSL_MC_SIZE,
 227           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 228           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 229         },
 230         { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
 231           CONFIG_SYS_FSL_NI_SIZE,
 232           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 233           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 234         },
 235         /* For QBMAN portal, only the first 64MB is cache-enabled */
 236         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 237           CONFIG_SYS_FSL_QBMAN_SIZE_1,
 238           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 239           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
 240         },
 241         { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 242           CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 243           CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
 244           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 245           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 246         },
 247         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 248           CONFIG_SYS_PCIE1_PHYS_SIZE,
 249           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 250           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 251         },
 252         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 253           CONFIG_SYS_PCIE2_PHYS_SIZE,
 254           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 255           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 256         },
 257 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 258         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 259           CONFIG_SYS_PCIE3_PHYS_SIZE,
 260           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 261           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 262         },
 263 #endif
 264 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
 265         { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
 266           CONFIG_SYS_PCIE4_PHYS_SIZE,
 267           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 268           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 269         },
 270 #endif
 271 #ifdef SYS_PCIE5_PHYS_ADDR
 272         { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
 273           SYS_PCIE5_PHYS_SIZE,
 274           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 275           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 276         },
 277 #endif
 278 #ifdef SYS_PCIE6_PHYS_ADDR
 279         { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
 280           SYS_PCIE6_PHYS_SIZE,
 281           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 282           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 283         },
 284 #endif
 285         { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
 286           CONFIG_SYS_FSL_WRIOP1_SIZE,
 287           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 288           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 289         },
 290         { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
 291           CONFIG_SYS_FSL_AIOP1_SIZE,
 292           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 293           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 294         },
 295         { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
 296           CONFIG_SYS_FSL_PEBUF_SIZE,
 297           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 298           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 299         },
 300         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 301           CONFIG_SYS_FSL_DRAM_SIZE2,
 302           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 303           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 304         },
 305 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 306         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 307           CONFIG_SYS_FSL_DRAM_SIZE3,
 308           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 309           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 310         },
 311 #endif
 312 #elif defined(CONFIG_FSL_LSCH2)
 313         { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
 314           CONFIG_SYS_FSL_BOOTROM_SIZE,
 315           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 316           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 317         },
 318         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 319           CONFIG_SYS_FSL_CCSR_SIZE,
 320           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 321           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 322         },
 323         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 324           SYS_FSL_OCRAM_SPACE_SIZE,
 325           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 326         },
 327         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 328           CONFIG_SYS_FSL_DCSR_SIZE,
 329           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 330           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 331         },
 332         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 333           CONFIG_SYS_FSL_QSPI_SIZE,
 334           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 335           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 336         },
 337 #ifdef CONFIG_FSL_IFC
 338         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 339           CONFIG_SYS_FSL_IFC_SIZE,
 340           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 341         },
 342 #endif
 343         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 344           CONFIG_SYS_FSL_DRAM_SIZE1,
 345           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 346           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 347         },
 348         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 349           CONFIG_SYS_FSL_QBMAN_SIZE,
 350           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 351           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 352         },
 353         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 354           CONFIG_SYS_FSL_DRAM_SIZE2,
 355           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 356           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 357         },
 358         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 359           CONFIG_SYS_PCIE1_PHYS_SIZE,
 360           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 361           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 362         },
 363         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 364           CONFIG_SYS_PCIE2_PHYS_SIZE,
 365           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 366           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 367         },
 368 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 369         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 370           CONFIG_SYS_PCIE3_PHYS_SIZE,
 371           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 372           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 373         },
 374 #endif
 375         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 376           CONFIG_SYS_FSL_DRAM_SIZE3,
 377           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 378           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 379         },
 380 #endif
 381 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 382         {},     /* space holder for secure mem */
 383 #endif
 384         {},
 385 };
 386
 387 struct mm_region *mem_map = early_map;
 388
 389 void cpu_name(char *name)
 390 {
 391         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 392         unsigned int i, svr, ver;
 393
 394         svr = gur_in32(&gur->svr);
 395         ver = SVR_SOC_VER(svr);
 396
 397         for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
 398                 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
 399                         strcpy(name, cpu_type_list[i].name);
 400 #ifdef CONFIG_ARCH_LX2160A
 401                         if (IS_C_PROCESSOR(svr))
 402                                 strcat(name, "C");
 403 #endif
 404
 405                         if (IS_E_PROCESSOR(svr))
 406                                 strcat(name, "E");
 407
 408                         sprintf(name + strlen(name), " Rev%d.%d",
 409                                 SVR_MAJ(svr), SVR_MIN(svr));
 410                         break;
 411                 }
 412
 413         if (i == ARRAY_SIZE(cpu_type_list))
 414                 strcpy(name, "unknown");
 415 }
 416
 417 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 418 /*
 419  * To start MMU before DDR is available, we create MMU table in SRAM.
 420  * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
 421  * levels of translation tables here to cover 40-bit address space.
 422  * We use 4KB granule size, with 40 bits physical address, T0SZ=24
 423  * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
 424  * Note, the debug print in cache_v8.c is not usable for debugging
 425  * these early MMU tables because UART is not yet available.
 426  */
 427 static inline void early_mmu_setup(void)
 428 {
 429         unsigned int el = current_el();
 430
 431         /* global data is already setup, no allocation yet */
 432         if (el == 3)
 433                 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
 434         else
 435                 gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
 436         gd->arch.tlb_fillptr = gd->arch.tlb_addr;
 437         gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
 438
 439         /* Create early page tables */
 440         setup_pgtables();
 441
 442         /* point TTBR to the new table */
 443         set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
 444                           get_tcr(el, NULL, NULL) &
 445                           ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
 446                           MEMORY_ATTRIBUTES);
 447
 448         set_sctlr(get_sctlr() | CR_M);
 449 }
 450
 451 static void fix_pcie_mmu_map(void)
 452 {
 453 #ifdef CONFIG_ARCH_LS2080A
 454         unsigned int i;
 455         u32 svr, ver;
 456         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 457
 458         svr = gur_in32(&gur->svr);
 459         ver = SVR_SOC_VER(svr);
 460
 461         /* Fix PCIE base and size for LS2088A */
 462         if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
 463             (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
 464             (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
 465                 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
 466                         switch (final_map[i].phys) {
 467                         case CONFIG_SYS_PCIE1_PHYS_ADDR:
 468                                 final_map[i].phys = 0x2000000000ULL;
 469                                 final_map[i].virt = 0x2000000000ULL;
 470                                 final_map[i].size = 0x800000000ULL;
 471                                 break;
 472                         case CONFIG_SYS_PCIE2_PHYS_ADDR:
 473                                 final_map[i].phys = 0x2800000000ULL;
 474                                 final_map[i].virt = 0x2800000000ULL;
 475                                 final_map[i].size = 0x800000000ULL;
 476                                 break;
 477 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 478                         case CONFIG_SYS_PCIE3_PHYS_ADDR:
 479                                 final_map[i].phys = 0x3000000000ULL;
 480                                 final_map[i].virt = 0x3000000000ULL;
 481                                 final_map[i].size = 0x800000000ULL;
 482                                 break;
 483 #endif
 484 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
 485                         case CONFIG_SYS_PCIE4_PHYS_ADDR:
 486                                 final_map[i].phys = 0x3800000000ULL;
 487                                 final_map[i].virt = 0x3800000000ULL;
 488                                 final_map[i].size = 0x800000000ULL;
 489                                 break;
 490 #endif
 491                         default:
 492                                 break;
 493                         }
 494                 }
 495         }
 496 #endif
 497 }
 498
 499 /*
 500  * The final tables look similar to early tables, but different in detail.
 501  * These tables are in DRAM. Sub tables are added to enable cache for
 502  * QBMan and OCRAM.
 503  *
 504  * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
 505  * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
 506  */
 507 static inline void final_mmu_setup(void)
 508 {
 509         u64 tlb_addr_save = gd->arch.tlb_addr;
 510         unsigned int el = current_el();
 511         int index;
 512
 513         /* fix the final_map before filling in the block entries */
 514         fix_pcie_mmu_map();
 515
 516         mem_map = final_map;
 517
 518         /* Update mapping for DDR to actual size */
 519         for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
 520                 /*
 521                  * Find the entry for DDR mapping and update the address and
 522                  * size. Zero-sized mapping will be skipped when creating MMU
 523                  * table.
 524                  */
 525                 switch (final_map[index].virt) {
 526                 case CONFIG_SYS_FSL_DRAM_BASE1:
 527                         final_map[index].virt = gd->bd->bi_dram[0].start;
 528                         final_map[index].phys = gd->bd->bi_dram[0].start;
 529                         final_map[index].size = gd->bd->bi_dram[0].size;
 530                         break;
 531 #ifdef CONFIG_SYS_FSL_DRAM_BASE2
 532                 case CONFIG_SYS_FSL_DRAM_BASE2:
 533 #if (CONFIG_NR_DRAM_BANKS >= 2)
 534                         final_map[index].virt = gd->bd->bi_dram[1].start;
 535                         final_map[index].phys = gd->bd->bi_dram[1].start;
 536                         final_map[index].size = gd->bd->bi_dram[1].size;
 537 #else
 538                         final_map[index].size = 0;
 539 #endif
 540                 break;
 541 #endif
 542 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 543                 case CONFIG_SYS_FSL_DRAM_BASE3:
 544 #if (CONFIG_NR_DRAM_BANKS >= 3)
 545                         final_map[index].virt = gd->bd->bi_dram[2].start;
 546                         final_map[index].phys = gd->bd->bi_dram[2].start;
 547                         final_map[index].size = gd->bd->bi_dram[2].size;
 548 #else
 549                         final_map[index].size = 0;
 550 #endif
 551                 break;
 552 #endif
 553                 default:
 554                         break;
 555                 }
 556         }
 557
 558 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 559         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 560                 if (el == 3) {
 561                         /*
 562                          * Only use gd->arch.secure_ram if the address is
 563                          * recalculated. Align to 4KB for MMU table.
 564                          */
 565                         /* put page tables in secure ram */
 566                         index = ARRAY_SIZE(final_map) - 2;
 567                         gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
 568                         final_map[index].virt = gd->arch.secure_ram & ~0x3;
 569                         final_map[index].phys = final_map[index].virt;
 570                         final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
 571                         final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
 572                         gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
 573                         tlb_addr_save = gd->arch.tlb_addr;
 574                 } else {
 575                         /* Use allocated (board_f.c) memory for TLB */
 576                         tlb_addr_save = gd->arch.tlb_allocated;
 577                         gd->arch.tlb_addr = tlb_addr_save;
 578                 }
 579         }
 580 #endif
 581
 582         /* Reset the fill ptr */
 583         gd->arch.tlb_fillptr = tlb_addr_save;
 584
 585         /* Create normal system page tables */
 586         setup_pgtables();
 587
 588         /* Create emergency page tables */
 589         gd->arch.tlb_addr = gd->arch.tlb_fillptr;
 590         gd->arch.tlb_emerg = gd->arch.tlb_addr;
 591         setup_pgtables();
 592         gd->arch.tlb_addr = tlb_addr_save;
 593
 594         /* Disable cache and MMU */
 595         dcache_disable();       /* TLBs are invalidated */
 596         invalidate_icache_all();
 597
 598         /* point TTBR to the new table */
 599         set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
 600                           MEMORY_ATTRIBUTES);
 601
 602         set_sctlr(get_sctlr() | CR_M);
 603 }
 604
 605 u64 get_page_table_size(void)
 606 {
 607         return 0x10000;
 608 }
 609
 610 int arch_cpu_init(void)
 611 {
 612         /*
 613          * This function is called before U-Boot relocates itself to speed up
 614          * on system running. It is not necessary to run if performance is not
 615          * critical. Skip if MMU is already enabled by SPL or other means.
 616          */
 617         if (get_sctlr() & CR_M)
 618                 return 0;
 619
 620         icache_enable();
 621         __asm_invalidate_dcache_all();
 622         __asm_invalidate_tlb_all();
 623         early_mmu_setup();
 624         set_sctlr(get_sctlr() | CR_C);
 625         return 0;
 626 }
 627
 628 void mmu_setup(void)
 629 {
 630         final_mmu_setup();
 631 }
 632
 633 /*
 634  * This function is called from common/board_r.c.
 635  * It recreates MMU table in main memory.
 636  */
 637 void enable_caches(void)
 638 {
 639         mmu_setup();
 640         __asm_invalidate_tlb_all();
 641         icache_enable();
 642         dcache_enable();
 643 }
 644 #endif  /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 645
 646 #ifdef CONFIG_TFABOOT
 647 enum boot_src __get_boot_src(u32 porsr1)
 648 {
 649         enum boot_src src = BOOT_SOURCE_RESERVED;
 650         u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
 651 #if !defined(CONFIG_NXP_LSCH3_2)
 652         u32 val;
 653 #endif
 654         debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
 655
 656 #if defined(CONFIG_FSL_LSCH3)
 657 #if defined(CONFIG_NXP_LSCH3_2)
 658         switch (rcw_src) {
 659         case RCW_SRC_SDHC1_VAL:
 660                 src = BOOT_SOURCE_SD_MMC;
 661         break;
 662         case RCW_SRC_SDHC2_VAL:
 663                 src = BOOT_SOURCE_SD_MMC2;
 664         break;
 665         case RCW_SRC_I2C1_VAL:
 666                 src = BOOT_SOURCE_I2C1_EXTENDED;
 667         break;
 668         case RCW_SRC_FLEXSPI_NAND2K_VAL:
 669                 src = BOOT_SOURCE_XSPI_NAND;
 670         break;
 671         case RCW_SRC_FLEXSPI_NAND4K_VAL:
 672                 src = BOOT_SOURCE_XSPI_NAND;
 673         break;
 674         case RCW_SRC_RESERVED_1_VAL:
 675                 src = BOOT_SOURCE_RESERVED;
 676         break;
 677         case RCW_SRC_FLEXSPI_NOR_24B:
 678                 src = BOOT_SOURCE_XSPI_NOR;
 679         break;
 680         default:
 681                 src = BOOT_SOURCE_RESERVED;
 682         }
 683 #else
 684         val = rcw_src & RCW_SRC_TYPE_MASK;
 685         if (val == RCW_SRC_NOR_VAL) {
 686                 val = rcw_src & NOR_TYPE_MASK;
 687
 688                 switch (val) {
 689                 case NOR_16B_VAL:
 690                 case NOR_32B_VAL:
 691                         src = BOOT_SOURCE_IFC_NOR;
 692                 break;
 693                 default:
 694                         src = BOOT_SOURCE_RESERVED;
 695                 }
 696         } else {
 697                 /* RCW SRC Serial Flash */
 698                 val = rcw_src & RCW_SRC_SERIAL_MASK;
 699                 switch (val) {
 700                 case RCW_SRC_QSPI_VAL:
 701                 /* RCW SRC Serial NOR (QSPI) */
 702                         src = BOOT_SOURCE_QSPI_NOR;
 703                         break;
 704                 case RCW_SRC_SD_CARD_VAL:
 705                 /* RCW SRC SD Card */
 706                         src = BOOT_SOURCE_SD_MMC;
 707                         break;
 708                 case RCW_SRC_EMMC_VAL:
 709                 /* RCW SRC EMMC */
 710                         src = BOOT_SOURCE_SD_MMC;
 711                         break;
 712                 case RCW_SRC_I2C1_VAL:
 713                 /* RCW SRC I2C1 Extended */
 714                         src = BOOT_SOURCE_I2C1_EXTENDED;
 715                         break;
 716                 default:
 717                         src = BOOT_SOURCE_RESERVED;
 718                 }
 719         }
 720 #endif
 721 #elif defined(CONFIG_FSL_LSCH2)
 722         /* RCW SRC NAND */
 723         val = rcw_src & RCW_SRC_NAND_MASK;
 724         if (val == RCW_SRC_NAND_VAL) {
 725                 val = rcw_src & NAND_RESERVED_MASK;
 726                 if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
 727                         src = BOOT_SOURCE_IFC_NAND;
 728
 729         } else {
 730                 /* RCW SRC NOR */
 731                 val = rcw_src & RCW_SRC_NOR_MASK;
 732                 if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
 733                         src = BOOT_SOURCE_IFC_NOR;
 734                 } else {
 735                         switch (rcw_src) {
 736                         case QSPI_VAL1:
 737                         case QSPI_VAL2:
 738                                 src = BOOT_SOURCE_QSPI_NOR;
 739                                 break;
 740                         case SD_VAL:
 741                                 src = BOOT_SOURCE_SD_MMC;
 742                                 break;
 743                         default:
 744                                 src = BOOT_SOURCE_RESERVED;
 745                         }
 746                 }
 747         }
 748 #endif
 749
 750         if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
 751                 src = BOOT_SOURCE_QSPI_NOR;
 752
 753         debug("%s: src 0x%x\n", __func__, src);
 754         return src;
 755 }
 756
 757 enum boot_src get_boot_src(void)
 758 {
 759         struct pt_regs regs;
 760         u32 porsr1 = 0;
 761
 762 #if defined(CONFIG_FSL_LSCH3)
 763         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 764 #elif defined(CONFIG_FSL_LSCH2)
 765         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 766 #endif
 767
 768         if (current_el() == 2) {
 769                 regs.regs[0] = SIP_SVC_RCW;
 770
 771                 smc_call(&regs);
 772                 if (!regs.regs[0])
 773                         porsr1 = regs.regs[1];
 774         }
 775
 776         if (current_el() == 3 || !porsr1) {
 777 #ifdef CONFIG_FSL_LSCH3
 778                 porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
 779 #elif defined(CONFIG_FSL_LSCH2)
 780                 porsr1 = in_be32(&gur->porsr1);
 781 #endif
 782         }
 783
 784         debug("%s: porsr1 0x%x\n", __func__, porsr1);
 785
 786         return __get_boot_src(porsr1);
 787 }
 788
 789 #ifdef CONFIG_ENV_IS_IN_MMC
 790 int mmc_get_env_dev(void)
 791 {
 792         enum boot_src src = get_boot_src();
 793         int dev = CONFIG_SYS_MMC_ENV_DEV;
 794
 795         switch (src) {
 796         case BOOT_SOURCE_SD_MMC:
 797                 dev = 0;
 798                 break;
 799         case BOOT_SOURCE_SD_MMC2:
 800                 dev = 1;
 801                 break;
 802         default:
 803                 break;
 804         }
 805
 806         return dev;
 807 }
 808 #endif
 809
 810 enum env_location env_get_location(enum env_operation op, int prio)
 811 {
 812         enum boot_src src = get_boot_src();
 813         enum env_location env_loc = ENVL_NOWHERE;
 814
 815         if (prio)
 816                 return ENVL_UNKNOWN;
 817
 818 #ifdef  CONFIG_ENV_IS_NOWHERE
 819         return env_loc;
 820 #endif
 821
 822         switch (src) {
 823         case BOOT_SOURCE_IFC_NOR:
 824                 env_loc = ENVL_FLASH;
 825                 break;
 826         case BOOT_SOURCE_QSPI_NOR:
 827                 /* FALLTHROUGH */
 828         case BOOT_SOURCE_XSPI_NOR:
 829                 env_loc = ENVL_SPI_FLASH;
 830                 break;
 831         case BOOT_SOURCE_IFC_NAND:
 832                 /* FALLTHROUGH */
 833         case BOOT_SOURCE_QSPI_NAND:
 834                 /* FALLTHROUGH */
 835         case BOOT_SOURCE_XSPI_NAND:
 836                 env_loc = ENVL_NAND;
 837                 break;
 838         case BOOT_SOURCE_SD_MMC:
 839                 /* FALLTHROUGH */
 840         case BOOT_SOURCE_SD_MMC2:
 841                 env_loc =  ENVL_MMC;
 842                 break;
 843         case BOOT_SOURCE_I2C1_EXTENDED:
 844                 /* FALLTHROUGH */
 845         default:
 846                 break;
 847         }
 848
 849         return env_loc;
 850 }
 851 #endif  /* CONFIG_TFABOOT */
 852
 853 u32 initiator_type(u32 cluster, int init_id)
 854 {
 855         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 856         u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
 857         u32 type = 0;
 858
 859         type = gur_in32(&gur->tp_ityp[idx]);
 860         if (type & TP_ITYP_AV)
 861                 return type;
 862
 863         return 0;
 864 }
 865
 866 u32 cpu_pos_mask(void)
 867 {
 868         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 869         int i = 0;
 870         u32 cluster, type, mask = 0;
 871
 872         do {
 873                 int j;
 874
 875                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 876                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 877                         type = initiator_type(cluster, j);
 878                         if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
 879                                 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
 880                 }
 881                 i++;
 882         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 883
 884         return mask;
 885 }
 886
 887 u32 cpu_mask(void)
 888 {
 889         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 890         int i = 0, count = 0;
 891         u32 cluster, type, mask = 0;
 892
 893         do {
 894                 int j;
 895
 896                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 897                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 898                         type = initiator_type(cluster, j);
 899                         if (type) {
 900                                 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
 901                                         mask |= 1 << count;
 902                                 count++;
 903                         }
 904                 }
 905                 i++;
 906         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 907
 908         return mask;
 909 }
 910
 911 /*
 912  * Return the number of cores on this SOC.
 913  */
 914 int cpu_numcores(void)
 915 {
 916         return hweight32(cpu_mask());
 917 }
 918
 919 int fsl_qoriq_core_to_cluster(unsigned int core)
 920 {
 921         struct ccsr_gur __iomem *gur =
 922                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 923         int i = 0, count = 0;
 924         u32 cluster;
 925
 926         do {
 927                 int j;
 928
 929                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 930                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 931                         if (initiator_type(cluster, j)) {
 932                                 if (count == core)
 933                                         return i;
 934                                 count++;
 935                         }
 936                 }
 937                 i++;
 938         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 939
 940         return -1;      /* cannot identify the cluster */
 941 }
 942
 943 u32 fsl_qoriq_core_to_type(unsigned int core)
 944 {
 945         struct ccsr_gur __iomem *gur =
 946                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 947         int i = 0, count = 0;
 948         u32 cluster, type;
 949
 950         do {
 951                 int j;
 952
 953                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 954                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 955                         type = initiator_type(cluster, j);
 956                         if (type) {
 957                                 if (count == core)
 958                                         return type;
 959                                 count++;
 960                         }
 961                 }
 962                 i++;
 963         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 964
 965         return -1;      /* cannot identify the cluster */
 966 }
 967
 968 #ifndef CONFIG_FSL_LSCH3
 969 uint get_svr(void)
 970 {
 971         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 972
 973         return gur_in32(&gur->svr);
 974 }
 975 #endif
 976
 977 #ifdef CONFIG_DISPLAY_CPUINFO
 978 int print_cpuinfo(void)
 979 {
 980         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 981         struct sys_info sysinfo;
 982         char buf[32];
 983         unsigned int i, core;
 984         u32 type, rcw, svr = gur_in32(&gur->svr);
 985
 986         puts("SoC: ");
 987
 988         cpu_name(buf);
 989         printf(" %s (0x%x)\n", buf, svr);
 990         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 991         get_sys_info(&sysinfo);
 992         puts("Clock Configuration:");
 993         for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
 994                 if (!(i % 3))
 995                         puts("\n       ");
 996                 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
 997                 printf("CPU%d(%s):%-4s MHz  ", core,
 998                        type == TY_ITYP_VER_A7 ? "A7 " :
 999                        (type == TY_ITYP_VER_A53 ? "A53" :
1000                        (type == TY_ITYP_VER_A57 ? "A57" :
1001                        (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
1002                        strmhz(buf, sysinfo.freq_processor[core]));
1003         }
1004         /* Display platform clock as Bus frequency. */
1005         printf("\n       Bus:      %-4s MHz  ",
1006                strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
1007         printf("DDR:      %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
1008 #ifdef CONFIG_SYS_DPAA_FMAN
1009         printf("  FMAN:     %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
1010 #endif
1011 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
1012         if (soc_has_dp_ddr()) {
1013                 printf("     DP-DDR:   %-4s MT/s",
1014                        strmhz(buf, sysinfo.freq_ddrbus2));
1015         }
1016 #endif
1017         puts("\n");
1018
1019         /*
1020          * Display the RCW, so that no one gets confused as to what RCW
1021          * we're actually using for this boot.
1022          */
1023         puts("Reset Configuration Word (RCW):");
1024         for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
1025                 rcw = gur_in32(&gur->rcwsr[i]);
1026                 if ((i % 4) == 0)
1027                         printf("\n       %08x:", i * 4);
1028                 printf(" %08x", rcw);
1029         }
1030         puts("\n");
1031
1032         return 0;
1033 }
1034 #endif
1035
1036 #ifdef CONFIG_FSL_ESDHC
1037 int cpu_mmc_init(bd_t *bis)
1038 {
1039         return fsl_esdhc_mmc_init(bis);
1040 }
1041 #endif
1042
1043 int cpu_eth_init(bd_t *bis)
1044 {
1045         int error = 0;
1046
1047 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1048         error = fsl_mc_ldpaa_init(bis);
1049 #endif
1050 #ifdef CONFIG_FMAN_ENET
1051         fm_standard_init(bis);
1052 #endif
1053         return error;
1054 }
1055
1056 static inline int check_psci(void)
1057 {
1058         unsigned int psci_ver;
1059
1060         psci_ver = sec_firmware_support_psci_version();
1061         if (psci_ver == PSCI_INVALID_VER)
1062                 return 1;
1063
1064         return 0;
1065 }
1066
1067 static void config_core_prefetch(void)
1068 {
1069         char *buf = NULL;
1070         char buffer[HWCONFIG_BUFFER_SIZE];
1071         const char *prefetch_arg = NULL;
1072         size_t arglen;
1073         unsigned int mask;
1074         struct pt_regs regs;
1075
1076         if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
1077                 buf = buffer;
1078         else
1079                 return;
1080
1081         prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
1082                                          &arglen, buf);
1083
1084         if (prefetch_arg) {
1085                 mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
1086                 if (mask & 0x1) {
1087                         printf("Core0 prefetch can't be disabled\n");
1088                         return;
1089                 }
1090
1091 #define SIP_PREFETCH_DISABLE_64 0xC200FF13
1092                 regs.regs[0] = SIP_PREFETCH_DISABLE_64;
1093                 regs.regs[1] = mask;
1094                 smc_call(&regs);
1095
1096                 if (regs.regs[0])
1097                         printf("Prefetch disable config failed for mask ");
1098                 else
1099                         printf("Prefetch disable config passed for mask ");
1100                 printf("0x%x\n", mask);
1101         }
1102 }
1103
1104 #ifdef CONFIG_PCIE_ECAM_GENERIC
1105 __weak void set_ecam_icids(void)
1106 {
1107 }
1108 #endif
1109
1110 int arch_early_init_r(void)
1111 {
1112 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
1113         u32 svr_dev_id;
1114         /*
1115          * erratum A009635 is valid only for LS2080A SoC and
1116          * its personalitiesi
1117          */
1118         svr_dev_id = get_svr();
1119         if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1120                 erratum_a009635();
1121 #endif
1122 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
1123         erratum_a009942_check_cpo();
1124 #endif
1125         if (check_psci()) {
1126                 debug("PSCI: PSCI does not exist.\n");
1127
1128                 /* if PSCI does not exist, boot secondary cores here */
1129                 if (fsl_layerscape_wake_seconday_cores())
1130                         printf("Did not wake secondary cores\n");
1131         }
1132
1133         config_core_prefetch();
1134
1135 #ifdef CONFIG_SYS_HAS_SERDES
1136         fsl_serdes_init();
1137 #endif
1138 #ifdef CONFIG_SYS_FSL_HAS_RGMII
1139         /* some dpmacs in armv8a based freescale layerscape SOCs can be
1140          * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
1141          * EC*_PMUX(rgmii) bits in RCW.
1142          * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
1143          * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
1144          * Now if a dpmac is enabled by serdes bits then it takes precedence
1145          * over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
1146          * that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
1147          * then the dpmac is SGMII and not RGMII.
1148          *
1149          * Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
1150          * fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
1151          * or not? if it is (fsl_serdes_init has already enabled the dpmac),
1152          * then don't enable it.
1153          */
1154         fsl_rgmii_init();
1155 #endif
1156 #ifdef CONFIG_FMAN_ENET
1157         fman_enet_init();
1158 #endif
1159 #ifdef CONFIG_SYS_DPAA_QBMAN
1160         setup_qbman_portals();
1161 #endif
1162 #ifdef CONFIG_PCIE_ECAM_GENERIC
1163         set_ecam_icids();
1164 #endif
1165         return 0;
1166 }
1167
1168 int timer_init(void)
1169 {
1170         u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
1171 #ifdef CONFIG_FSL_LSCH3
1172         u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
1173 #endif
1174 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1175         defined(CONFIG_ARCH_LS1028A)
1176         u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
1177         u32 svr_dev_id;
1178 #endif
1179 #ifdef COUNTER_FREQUENCY_REAL
1180         unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
1181
1182         /* Update with accurate clock frequency */
1183         if (current_el() == 3)
1184                 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
1185 #endif
1186
1187 #ifdef CONFIG_FSL_LSCH3
1188         /* Enable timebase for all clusters.
1189          * It is safe to do so even some clusters are not enabled.
1190          */
1191         out_le32(cltbenr, 0xf);
1192 #endif
1193
1194 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1195         defined(CONFIG_ARCH_LS1028A)
1196         /*
1197          * In certain Layerscape SoCs, the clock for each core's
1198          * has an enable bit in the PMU Physical Core Time Base Enable
1199          * Register (PCTBENR), which allows the watchdog to operate.
1200          */
1201         setbits_le32(pctbenr, 0xff);
1202         /*
1203          * For LS2080A SoC and its personalities, timer controller
1204          * offset is different
1205          */
1206         svr_dev_id = get_svr();
1207         if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1208                 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
1209
1210 #endif
1211
1212         /* Enable clock for timer
1213          * This is a global setting.
1214          */
1215         out_le32(cntcr, 0x1);
1216
1217         return 0;
1218 }
1219
1220 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
1221
1222 void __efi_runtime reset_cpu(ulong addr)
1223 {
1224         u32 val;
1225
1226 #ifdef CONFIG_ARCH_LX2160A
1227         val = in_le32(rstcr);
1228         val |= 0x01;
1229         out_le32(rstcr, val);
1230 #else
1231         /* Raise RESET_REQ_B */
1232         val = scfg_in32(rstcr);
1233         val |= 0x02;
1234         scfg_out32(rstcr, val);
1235 #endif
1236 }
1237
1238 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET)
1239
1240 void __efi_runtime EFIAPI efi_reset_system(
1241                        enum efi_reset_type reset_type,
1242                        efi_status_t reset_status,
1243                        unsigned long data_size, void *reset_data)
1244 {
1245         switch (reset_type) {
1246         case EFI_RESET_COLD:
1247         case EFI_RESET_WARM:
1248         case EFI_RESET_PLATFORM_SPECIFIC:
1249                 reset_cpu(0);
1250                 break;
1251         case EFI_RESET_SHUTDOWN:
1252                 /* Nothing we can do */
1253                 break;
1254         }
1255
1256         while (1) { }
1257 }
1258
1259 efi_status_t efi_reset_system_init(void)
1260 {
1261         return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
1262 }
1263
1264 #endif
1265
1266 /*
1267  * Calculate reserved memory with given memory bank
1268  * Return aligned memory size on success
1269  * Return (ram_size + needed size) for failure
1270  */
1271 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
1272 {
1273         phys_size_t ram_top = ram_size;
1274
1275 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1276         ram_top = mc_get_dram_block_size();
1277         if (ram_top > ram_size)
1278                 return ram_size + ram_top;
1279
1280         ram_top = ram_size - ram_top;
1281         /* The start address of MC reserved memory needs to be aligned. */
1282         ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
1283 #endif
1284
1285         return ram_size - ram_top;
1286 }
1287
1288 phys_size_t get_effective_memsize(void)
1289 {
1290         phys_size_t ea_size, rem = 0;
1291
1292         /*
1293          * For ARMv8 SoCs, DDR memory is split into two or three regions. The
1294          * first region is 2GB space at 0x8000_0000. Secure memory needs to
1295          * allocated from first region. If the memory extends to  the second
1296          * region (or the third region if applicable), Management Complex (MC)
1297          * memory should be put into the highest region, i.e. the end of DDR
1298          * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
1299          * U-Boot doesn't relocate itself into higher address. Should DDR be
1300          * configured to skip the first region, this function needs to be
1301          * adjusted.
1302          */
1303         if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
1304                 ea_size = CONFIG_MAX_MEM_MAPPED;
1305                 rem = gd->ram_size - ea_size;
1306         } else {
1307                 ea_size = gd->ram_size;
1308         }
1309
1310 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1311         /* Check if we have enough space for secure memory */
1312         if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
1313                 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1314         else
1315                 printf("Error: No enough space for secure memory.\n");
1316 #endif
1317         /* Check if we have enough memory for MC */
1318         if (rem < board_reserve_ram_top(rem)) {
1319                 /* Not enough memory in high region to reserve */
1320                 if (ea_size > board_reserve_ram_top(ea_size))
1321                         ea_size -= board_reserve_ram_top(ea_size);
1322                 else
1323                         printf("Error: No enough space for reserved memory.\n");
1324         }
1325
1326         return ea_size;
1327 }
1328
1329 #ifdef CONFIG_TFABOOT
1330 phys_size_t tfa_get_dram_size(void)
1331 {
1332         struct pt_regs regs;
1333         phys_size_t dram_size = 0;
1334
1335         regs.regs[0] = SMC_DRAM_BANK_INFO;
1336         regs.regs[1] = -1;
1337
1338         smc_call(&regs);
1339         if (regs.regs[0])
1340                 return 0;
1341
1342         dram_size = regs.regs[1];
1343         return dram_size;
1344 }
1345
1346 static int tfa_dram_init_banksize(void)
1347 {
1348         int i = 0, ret = 0;
1349         struct pt_regs regs;
1350         phys_size_t dram_size = tfa_get_dram_size();
1351
1352         debug("dram_size %llx\n", dram_size);
1353
1354         if (!dram_size)
1355                 return -EINVAL;
1356
1357         do {
1358                 regs.regs[0] = SMC_DRAM_BANK_INFO;
1359                 regs.regs[1] = i;
1360
1361                 smc_call(&regs);
1362                 if (regs.regs[0]) {
1363                         ret = -EINVAL;
1364                         break;
1365                 }
1366
1367                 debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
1368                       regs.regs[2]);
1369                 gd->bd->bi_dram[i].start = regs.regs[1];
1370                 gd->bd->bi_dram[i].size = regs.regs[2];
1371
1372                 dram_size -= gd->bd->bi_dram[i].size;
1373
1374                 i++;
1375         } while (dram_size);
1376
1377         if (i > 0)
1378                 ret = 0;
1379
1380 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1381         /* Assign memory for MC */
1382 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1383         if (gd->bd->bi_dram[2].size >=
1384             board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1385                 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1386                             gd->bd->bi_dram[2].size -
1387                             board_reserve_ram_top(gd->bd->bi_dram[2].size);
1388         } else
1389 #endif
1390         {
1391                 if (gd->bd->bi_dram[1].size >=
1392                     board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1393                         gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1394                                 gd->bd->bi_dram[1].size -
1395                                 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1396                 } else if (gd->bd->bi_dram[0].size >
1397                            board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1398                         gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1399                                 gd->bd->bi_dram[0].size -
1400                                 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1401                 }
1402         }
1403 #endif  /* CONFIG_FSL_MC_ENET */
1404
1405         return ret;
1406 }
1407 #endif
1408
1409 int dram_init_banksize(void)
1410 {
1411 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1412         phys_size_t dp_ddr_size;
1413 #endif
1414
1415 #ifdef CONFIG_TFABOOT
1416         if (!tfa_dram_init_banksize())
1417                 return 0;
1418 #endif
1419         /*
1420          * gd->ram_size has the total size of DDR memory, less reserved secure
1421          * memory. The DDR extends from low region to high region(s) presuming
1422          * no hole is created with DDR configuration. gd->arch.secure_ram tracks
1423          * the location of secure memory. gd->arch.resv_ram tracks the location
1424          * of reserved memory for Management Complex (MC). Because gd->ram_size
1425          * is reduced by this function if secure memory is reserved, checking
1426          * gd->arch.secure_ram should be done to avoid running it repeatedly.
1427          */
1428
1429 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1430         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
1431                 debug("No need to run again, skip %s\n", __func__);
1432
1433                 return 0;
1434         }
1435 #endif
1436
1437         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
1438         if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
1439                 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
1440                 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
1441                 gd->bd->bi_dram[1].size = gd->ram_size -
1442                                           CONFIG_SYS_DDR_BLOCK1_SIZE;
1443 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1444                 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
1445                         gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
1446                         gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
1447                                                   CONFIG_SYS_DDR_BLOCK2_SIZE;
1448                         gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
1449                 }
1450 #endif
1451         } else {
1452                 gd->bd->bi_dram[0].size = gd->ram_size;
1453         }
1454 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1455         if (gd->bd->bi_dram[0].size >
1456                                 CONFIG_SYS_MEM_RESERVE_SECURE) {
1457                 gd->bd->bi_dram[0].size -=
1458                                 CONFIG_SYS_MEM_RESERVE_SECURE;
1459                 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
1460                                       gd->bd->bi_dram[0].size;
1461                 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
1462                 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1463         }
1464 #endif  /* CONFIG_SYS_MEM_RESERVE_SECURE */
1465
1466 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1467         /* Assign memory for MC */
1468 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1469         if (gd->bd->bi_dram[2].size >=
1470             board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1471                 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1472                             gd->bd->bi_dram[2].size -
1473                             board_reserve_ram_top(gd->bd->bi_dram[2].size);
1474         } else
1475 #endif
1476         {
1477                 if (gd->bd->bi_dram[1].size >=
1478                     board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1479                         gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1480                                 gd->bd->bi_dram[1].size -
1481                                 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1482                 } else if (gd->bd->bi_dram[0].size >
1483                            board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1484                         gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1485                                 gd->bd->bi_dram[0].size -
1486                                 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1487                 }
1488         }
1489 #endif  /* CONFIG_FSL_MC_ENET */
1490
1491 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1492 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1493 #error "This SoC shouldn't have DP DDR"
1494 #endif
1495         if (soc_has_dp_ddr()) {
1496                 /* initialize DP-DDR here */
1497                 puts("DP-DDR:  ");
1498                 /*
1499                  * DDR controller use 0 as the base address for binding.
1500                  * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
1501                  */
1502                 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
1503                                           CONFIG_DP_DDR_CTRL,
1504                                           CONFIG_DP_DDR_NUM_CTRLS,
1505                                           CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
1506                                           NULL, NULL, NULL);
1507                 if (dp_ddr_size) {
1508                         gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
1509                         gd->bd->bi_dram[2].size = dp_ddr_size;
1510                 } else {
1511                         puts("Not detected");
1512                 }
1513         }
1514 #endif
1515
1516 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1517         debug("%s is called. gd->ram_size is reduced to %lu\n",
1518               __func__, (ulong)gd->ram_size);
1519 #endif
1520
1521         return 0;
1522 }
1523
1524 #if CONFIG_IS_ENABLED(EFI_LOADER)
1525 void efi_add_known_memory(void)
1526 {
1527         int i;
1528         phys_addr_t ram_start, start;
1529         phys_size_t ram_size;
1530         u64 pages;
1531
1532         /* Add RAM */
1533         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
1534 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1535 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1536 #error "This SoC shouldn't have DP DDR"
1537 #endif
1538                 if (i == 2)
1539                         continue;       /* skip DP-DDR */
1540 #endif
1541                 ram_start = gd->bd->bi_dram[i].start;
1542                 ram_size = gd->bd->bi_dram[i].size;
1543 #ifdef CONFIG_RESV_RAM
1544                 if (gd->arch.resv_ram >= ram_start &&
1545                     gd->arch.resv_ram < ram_start + ram_size)
1546                         ram_size = gd->arch.resv_ram - ram_start;
1547 #endif
1548                 start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
1549                 pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
1550
1551                 efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY,
1552                                    false);
1553         }
1554 }
1555 #endif
1556
1557 /*
1558  * Before DDR size is known, early MMU table have DDR mapped as device memory
1559  * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
1560  * needs to be set for these mappings.
1561  * If a special case configures DDR with holes in the mapping, the holes need
1562  * to be marked as invalid. This is not implemented in this function.
1563  */
1564 void update_early_mmu_table(void)
1565 {
1566         if (!gd->arch.tlb_addr)
1567                 return;
1568
1569         if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
1570                 mmu_change_region_attr(
1571                                         CONFIG_SYS_SDRAM_BASE,
1572                                         gd->ram_size,
1573                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1574                                         PTE_BLOCK_OUTER_SHARE           |
1575                                         PTE_BLOCK_NS                    |
1576                                         PTE_TYPE_VALID);
1577         } else {
1578                 mmu_change_region_attr(
1579                                         CONFIG_SYS_SDRAM_BASE,
1580                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
1581                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1582                                         PTE_BLOCK_OUTER_SHARE           |
1583                                         PTE_BLOCK_NS                    |
1584                                         PTE_TYPE_VALID);
1585 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1586 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
1587 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
1588 #endif
1589                 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
1590                     CONFIG_SYS_DDR_BLOCK2_SIZE) {
1591                         mmu_change_region_attr(
1592                                         CONFIG_SYS_DDR_BLOCK2_BASE,
1593                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
1594                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1595                                         PTE_BLOCK_OUTER_SHARE           |
1596                                         PTE_BLOCK_NS                    |
1597                                         PTE_TYPE_VALID);
1598                         mmu_change_region_attr(
1599                                         CONFIG_SYS_DDR_BLOCK3_BASE,
1600                                         gd->ram_size -
1601                                         CONFIG_SYS_DDR_BLOCK1_SIZE -
1602                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
1603                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1604                                         PTE_BLOCK_OUTER_SHARE           |
1605                                         PTE_BLOCK_NS                    |
1606                                         PTE_TYPE_VALID);
1607                 } else
1608 #endif
1609                 {
1610                         mmu_change_region_attr(
1611                                         CONFIG_SYS_DDR_BLOCK2_BASE,
1612                                         gd->ram_size -
1613                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
1614                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1615                                         PTE_BLOCK_OUTER_SHARE           |
1616                                         PTE_BLOCK_NS                    |
1617                                         PTE_TYPE_VALID);
1618                 }
1619         }
1620 }
1621
1622 __weak int dram_init(void)
1623 {
1624         fsl_initdram();
1625 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
1626         defined(CONFIG_SPL_BUILD)
1627         /* This will break-before-make MMU for DDR */
1628         update_early_mmu_table();
1629 #endif
1630
1631         return 0;
1632 }