arch/arm/cpu/armv8/fsl-layerscape/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017-2019 NXP
   4  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <common.h>
   8 #include <env.h>
   9 #include <fsl_ddr_sdram.h>
  10 #include <asm/io.h>
  11 #include <linux/errno.h>
  12 #include <asm/system.h>
  13 #include <fm_eth.h>
  14 #include <asm/armv8/mmu.h>
  15 #include <asm/io.h>
  16 #include <asm/arch/fsl_serdes.h>
  17 #include <asm/arch/soc.h>
  18 #include <asm/arch/cpu.h>
  19 #include <asm/arch/speed.h>
  20 #include <fsl_immap.h>
  21 #include <asm/arch/mp.h>
  22 #include <efi_loader.h>
  23 #include <fsl-mc/fsl_mc.h>
  24 #ifdef CONFIG_FSL_ESDHC
  25 #include <fsl_esdhc.h>
  26 #endif
  27 #include <asm/armv8/sec_firmware.h>
  28 #ifdef CONFIG_SYS_FSL_DDR
  29 #include <fsl_ddr.h>
  30 #endif
  31 #include <asm/arch/clock.h>
  32 #include <hwconfig.h>
  33 #include <fsl_qbman.h>
  34
  35 #ifdef CONFIG_TFABOOT
  36 #include <env_internal.h>
  37 #ifdef CONFIG_CHAIN_OF_TRUST
  38 #include <fsl_validate.h>
  39 #endif
  40 #endif
  41
  42 DECLARE_GLOBAL_DATA_PTR;
  43
  44 static struct cpu_type cpu_type_list[] = {
  45         CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
  46         CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
  47         CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
  48         CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
  49         CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
  50         CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
  51         CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
  52         CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
  53         CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
  54         CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
  55         CPU_TYPE_ENTRY(LS1043A, LS1043A_P23, 4),
  56         CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
  57         CPU_TYPE_ENTRY(LS1023A, LS1023A_P23, 2),
  58         CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
  59         CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
  60         CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
  61         CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
  62         CPU_TYPE_ENTRY(LS1017A, LS1017A, 1),
  63         CPU_TYPE_ENTRY(LS1018A, LS1018A, 1),
  64         CPU_TYPE_ENTRY(LS1027A, LS1027A, 2),
  65         CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
  66         CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
  67         CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
  68         CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
  69         CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
  70         CPU_TYPE_ENTRY(LX2160A, LX2160A, 16),
  71         CPU_TYPE_ENTRY(LX2120A, LX2120A, 12),
  72         CPU_TYPE_ENTRY(LX2080A, LX2080A, 8),
  73 };
  74
  75 #define EARLY_PGTABLE_SIZE 0x5000
  76 static struct mm_region early_map[] = {
  77 #ifdef CONFIG_FSL_LSCH3
  78         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
  79           CONFIG_SYS_FSL_CCSR_SIZE,
  80           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  81           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  82         },
  83         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  84           SYS_FSL_OCRAM_SPACE_SIZE,
  85           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
  86         },
  87         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
  88           CONFIG_SYS_FSL_QSPI_SIZE1,
  89           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
  90 #ifdef CONFIG_FSL_IFC
  91         /* For IFC Region #1, only the first 4MB is cache-enabled */
  92         { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
  93           CONFIG_SYS_FSL_IFC_SIZE1_1,
  94           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
  95         },
  96         { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
  97           CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
  98           CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
  99           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 100         },
 101         { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
 102           CONFIG_SYS_FSL_IFC_SIZE1,
 103           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 104         },
 105 #endif
 106         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 107           CONFIG_SYS_FSL_DRAM_SIZE1,
 108 #if defined(CONFIG_TFABOOT) || \
 109         (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 110           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 111 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
 112           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 113 #endif
 114           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 115         },
 116 #ifdef CONFIG_FSL_IFC
 117         /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
 118         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 119           CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
 120           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 121         },
 122 #endif
 123         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 124           CONFIG_SYS_FSL_DCSR_SIZE,
 125           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 126           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 127         },
 128         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 129           CONFIG_SYS_FSL_DRAM_SIZE2,
 130           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 131           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 132         },
 133 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 134         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 135           CONFIG_SYS_FSL_DRAM_SIZE3,
 136           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 137           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 138         },
 139 #endif
 140 #elif defined(CONFIG_FSL_LSCH2)
 141         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 142           CONFIG_SYS_FSL_CCSR_SIZE,
 143           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 144           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 145         },
 146         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 147           SYS_FSL_OCRAM_SPACE_SIZE,
 148           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 149         },
 150         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 151           CONFIG_SYS_FSL_DCSR_SIZE,
 152           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 153           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 154         },
 155         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 156           CONFIG_SYS_FSL_QSPI_SIZE,
 157           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 158         },
 159 #ifdef CONFIG_FSL_IFC
 160         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 161           CONFIG_SYS_FSL_IFC_SIZE,
 162           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 163         },
 164 #endif
 165         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 166           CONFIG_SYS_FSL_DRAM_SIZE1,
 167 #if defined(CONFIG_TFABOOT) || \
 168         (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 169           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 170 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
 171           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 172 #endif
 173           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 174         },
 175         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 176           CONFIG_SYS_FSL_DRAM_SIZE2,
 177           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 178           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 179         },
 180 #endif
 181         {},     /* list terminator */
 182 };
 183
 184 static struct mm_region final_map[] = {
 185 #ifdef CONFIG_FSL_LSCH3
 186         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 187           CONFIG_SYS_FSL_CCSR_SIZE,
 188           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 189           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 190         },
 191         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 192           SYS_FSL_OCRAM_SPACE_SIZE,
 193           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 194         },
 195         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 196           CONFIG_SYS_FSL_DRAM_SIZE1,
 197           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 198           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 199         },
 200         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
 201           CONFIG_SYS_FSL_QSPI_SIZE1,
 202           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 203           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 204         },
 205         { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
 206           CONFIG_SYS_FSL_QSPI_SIZE2,
 207           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 208           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 209         },
 210 #ifdef CONFIG_FSL_IFC
 211         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 212           CONFIG_SYS_FSL_IFC_SIZE2,
 213           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 214           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 215         },
 216 #endif
 217         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 218           CONFIG_SYS_FSL_DCSR_SIZE,
 219           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 220           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 221         },
 222         { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
 223           CONFIG_SYS_FSL_MC_SIZE,
 224           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 225           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 226         },
 227         { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
 228           CONFIG_SYS_FSL_NI_SIZE,
 229           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 230           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 231         },
 232         /* For QBMAN portal, only the first 64MB is cache-enabled */
 233         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 234           CONFIG_SYS_FSL_QBMAN_SIZE_1,
 235           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 236           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
 237         },
 238         { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 239           CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 240           CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
 241           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 242           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 243         },
 244         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 245           CONFIG_SYS_PCIE1_PHYS_SIZE,
 246           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 247           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 248         },
 249         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 250           CONFIG_SYS_PCIE2_PHYS_SIZE,
 251           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 252           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 253         },
 254 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 255         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 256           CONFIG_SYS_PCIE3_PHYS_SIZE,
 257           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 258           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 259         },
 260 #endif
 261 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
 262         { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
 263           CONFIG_SYS_PCIE4_PHYS_SIZE,
 264           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 265           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 266         },
 267 #endif
 268 #ifdef SYS_PCIE5_PHYS_ADDR
 269         { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
 270           SYS_PCIE5_PHYS_SIZE,
 271           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 272           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 273         },
 274 #endif
 275 #ifdef SYS_PCIE6_PHYS_ADDR
 276         { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
 277           SYS_PCIE6_PHYS_SIZE,
 278           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 279           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 280         },
 281 #endif
 282         { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
 283           CONFIG_SYS_FSL_WRIOP1_SIZE,
 284           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 285           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 286         },
 287         { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
 288           CONFIG_SYS_FSL_AIOP1_SIZE,
 289           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 290           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 291         },
 292         { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
 293           CONFIG_SYS_FSL_PEBUF_SIZE,
 294           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 295           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 296         },
 297         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 298           CONFIG_SYS_FSL_DRAM_SIZE2,
 299           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 300           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 301         },
 302 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 303         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 304           CONFIG_SYS_FSL_DRAM_SIZE3,
 305           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 306           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 307         },
 308 #endif
 309 #elif defined(CONFIG_FSL_LSCH2)
 310         { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
 311           CONFIG_SYS_FSL_BOOTROM_SIZE,
 312           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 313           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 314         },
 315         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 316           CONFIG_SYS_FSL_CCSR_SIZE,
 317           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 318           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 319         },
 320         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 321           SYS_FSL_OCRAM_SPACE_SIZE,
 322           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 323         },
 324         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 325           CONFIG_SYS_FSL_DCSR_SIZE,
 326           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 327           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 328         },
 329         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 330           CONFIG_SYS_FSL_QSPI_SIZE,
 331           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 332           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 333         },
 334 #ifdef CONFIG_FSL_IFC
 335         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 336           CONFIG_SYS_FSL_IFC_SIZE,
 337           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 338         },
 339 #endif
 340         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 341           CONFIG_SYS_FSL_DRAM_SIZE1,
 342           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 343           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 344         },
 345         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 346           CONFIG_SYS_FSL_QBMAN_SIZE,
 347           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 348           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 349         },
 350         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 351           CONFIG_SYS_FSL_DRAM_SIZE2,
 352           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 353           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 354         },
 355         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 356           CONFIG_SYS_PCIE1_PHYS_SIZE,
 357           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 358           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 359         },
 360         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 361           CONFIG_SYS_PCIE2_PHYS_SIZE,
 362           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 363           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 364         },
 365 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 366         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 367           CONFIG_SYS_PCIE3_PHYS_SIZE,
 368           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 369           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 370         },
 371 #endif
 372         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 373           CONFIG_SYS_FSL_DRAM_SIZE3,
 374           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 375           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 376         },
 377 #endif
 378 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 379         {},     /* space holder for secure mem */
 380 #endif
 381         {},
 382 };
 383
 384 struct mm_region *mem_map = early_map;
 385
 386 void cpu_name(char *name)
 387 {
 388         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 389         unsigned int i, svr, ver;
 390
 391         svr = gur_in32(&gur->svr);
 392         ver = SVR_SOC_VER(svr);
 393
 394         for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
 395                 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
 396                         strcpy(name, cpu_type_list[i].name);
 397 #ifdef CONFIG_ARCH_LX2160A
 398                         if (IS_C_PROCESSOR(svr))
 399                                 strcat(name, "C");
 400 #endif
 401
 402                         if (IS_E_PROCESSOR(svr))
 403                                 strcat(name, "E");
 404
 405                         sprintf(name + strlen(name), " Rev%d.%d",
 406                                 SVR_MAJ(svr), SVR_MIN(svr));
 407                         break;
 408                 }
 409
 410         if (i == ARRAY_SIZE(cpu_type_list))
 411                 strcpy(name, "unknown");
 412 }
 413
 414 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 415 /*
 416  * To start MMU before DDR is available, we create MMU table in SRAM.
 417  * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
 418  * levels of translation tables here to cover 40-bit address space.
 419  * We use 4KB granule size, with 40 bits physical address, T0SZ=24
 420  * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
 421  * Note, the debug print in cache_v8.c is not usable for debugging
 422  * these early MMU tables because UART is not yet available.
 423  */
 424 static inline void early_mmu_setup(void)
 425 {
 426         unsigned int el = current_el();
 427
 428         /* global data is already setup, no allocation yet */
 429         if (el == 3)
 430                 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
 431         else
 432                 gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
 433         gd->arch.tlb_fillptr = gd->arch.tlb_addr;
 434         gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
 435
 436         /* Create early page tables */
 437         setup_pgtables();
 438
 439         /* point TTBR to the new table */
 440         set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
 441                           get_tcr(el, NULL, NULL) &
 442                           ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
 443                           MEMORY_ATTRIBUTES);
 444
 445         set_sctlr(get_sctlr() | CR_M);
 446 }
 447
 448 static void fix_pcie_mmu_map(void)
 449 {
 450 #ifdef CONFIG_ARCH_LS2080A
 451         unsigned int i;
 452         u32 svr, ver;
 453         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 454
 455         svr = gur_in32(&gur->svr);
 456         ver = SVR_SOC_VER(svr);
 457
 458         /* Fix PCIE base and size for LS2088A */
 459         if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
 460             (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
 461             (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
 462                 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
 463                         switch (final_map[i].phys) {
 464                         case CONFIG_SYS_PCIE1_PHYS_ADDR:
 465                                 final_map[i].phys = 0x2000000000ULL;
 466                                 final_map[i].virt = 0x2000000000ULL;
 467                                 final_map[i].size = 0x800000000ULL;
 468                                 break;
 469                         case CONFIG_SYS_PCIE2_PHYS_ADDR:
 470                                 final_map[i].phys = 0x2800000000ULL;
 471                                 final_map[i].virt = 0x2800000000ULL;
 472                                 final_map[i].size = 0x800000000ULL;
 473                                 break;
 474 #ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
 475                         case CONFIG_SYS_PCIE3_PHYS_ADDR:
 476                                 final_map[i].phys = 0x3000000000ULL;
 477                                 final_map[i].virt = 0x3000000000ULL;
 478                                 final_map[i].size = 0x800000000ULL;
 479                                 break;
 480 #endif
 481 #ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
 482                         case CONFIG_SYS_PCIE4_PHYS_ADDR:
 483                                 final_map[i].phys = 0x3800000000ULL;
 484                                 final_map[i].virt = 0x3800000000ULL;
 485                                 final_map[i].size = 0x800000000ULL;
 486                                 break;
 487 #endif
 488                         default:
 489                                 break;
 490                         }
 491                 }
 492         }
 493 #endif
 494 }
 495
 496 /*
 497  * The final tables look similar to early tables, but different in detail.
 498  * These tables are in DRAM. Sub tables are added to enable cache for
 499  * QBMan and OCRAM.
 500  *
 501  * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
 502  * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
 503  */
 504 static inline void final_mmu_setup(void)
 505 {
 506         u64 tlb_addr_save = gd->arch.tlb_addr;
 507         unsigned int el = current_el();
 508         int index;
 509
 510         /* fix the final_map before filling in the block entries */
 511         fix_pcie_mmu_map();
 512
 513         mem_map = final_map;
 514
 515         /* Update mapping for DDR to actual size */
 516         for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
 517                 /*
 518                  * Find the entry for DDR mapping and update the address and
 519                  * size. Zero-sized mapping will be skipped when creating MMU
 520                  * table.
 521                  */
 522                 switch (final_map[index].virt) {
 523                 case CONFIG_SYS_FSL_DRAM_BASE1:
 524                         final_map[index].virt = gd->bd->bi_dram[0].start;
 525                         final_map[index].phys = gd->bd->bi_dram[0].start;
 526                         final_map[index].size = gd->bd->bi_dram[0].size;
 527                         break;
 528 #ifdef CONFIG_SYS_FSL_DRAM_BASE2
 529                 case CONFIG_SYS_FSL_DRAM_BASE2:
 530 #if (CONFIG_NR_DRAM_BANKS >= 2)
 531                         final_map[index].virt = gd->bd->bi_dram[1].start;
 532                         final_map[index].phys = gd->bd->bi_dram[1].start;
 533                         final_map[index].size = gd->bd->bi_dram[1].size;
 534 #else
 535                         final_map[index].size = 0;
 536 #endif
 537                 break;
 538 #endif
 539 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 540                 case CONFIG_SYS_FSL_DRAM_BASE3:
 541 #if (CONFIG_NR_DRAM_BANKS >= 3)
 542                         final_map[index].virt = gd->bd->bi_dram[2].start;
 543                         final_map[index].phys = gd->bd->bi_dram[2].start;
 544                         final_map[index].size = gd->bd->bi_dram[2].size;
 545 #else
 546                         final_map[index].size = 0;
 547 #endif
 548                 break;
 549 #endif
 550                 default:
 551                         break;
 552                 }
 553         }
 554
 555 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 556         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 557                 if (el == 3) {
 558                         /*
 559                          * Only use gd->arch.secure_ram if the address is
 560                          * recalculated. Align to 4KB for MMU table.
 561                          */
 562                         /* put page tables in secure ram */
 563                         index = ARRAY_SIZE(final_map) - 2;
 564                         gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
 565                         final_map[index].virt = gd->arch.secure_ram & ~0x3;
 566                         final_map[index].phys = final_map[index].virt;
 567                         final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
 568                         final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
 569                         gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
 570                         tlb_addr_save = gd->arch.tlb_addr;
 571                 } else {
 572                         /* Use allocated (board_f.c) memory for TLB */
 573                         tlb_addr_save = gd->arch.tlb_allocated;
 574                         gd->arch.tlb_addr = tlb_addr_save;
 575                 }
 576         }
 577 #endif
 578
 579         /* Reset the fill ptr */
 580         gd->arch.tlb_fillptr = tlb_addr_save;
 581
 582         /* Create normal system page tables */
 583         setup_pgtables();
 584
 585         /* Create emergency page tables */
 586         gd->arch.tlb_addr = gd->arch.tlb_fillptr;
 587         gd->arch.tlb_emerg = gd->arch.tlb_addr;
 588         setup_pgtables();
 589         gd->arch.tlb_addr = tlb_addr_save;
 590
 591         /* Disable cache and MMU */
 592         dcache_disable();       /* TLBs are invalidated */
 593         invalidate_icache_all();
 594
 595         /* point TTBR to the new table */
 596         set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
 597                           MEMORY_ATTRIBUTES);
 598
 599         set_sctlr(get_sctlr() | CR_M);
 600 }
 601
 602 u64 get_page_table_size(void)
 603 {
 604         return 0x10000;
 605 }
 606
 607 int arch_cpu_init(void)
 608 {
 609         /*
 610          * This function is called before U-Boot relocates itself to speed up
 611          * on system running. It is not necessary to run if performance is not
 612          * critical. Skip if MMU is already enabled by SPL or other means.
 613          */
 614         if (get_sctlr() & CR_M)
 615                 return 0;
 616
 617         icache_enable();
 618         __asm_invalidate_dcache_all();
 619         __asm_invalidate_tlb_all();
 620         early_mmu_setup();
 621         set_sctlr(get_sctlr() | CR_C);
 622         return 0;
 623 }
 624
 625 void mmu_setup(void)
 626 {
 627         final_mmu_setup();
 628 }
 629
 630 /*
 631  * This function is called from common/board_r.c.
 632  * It recreates MMU table in main memory.
 633  */
 634 void enable_caches(void)
 635 {
 636         mmu_setup();
 637         __asm_invalidate_tlb_all();
 638         icache_enable();
 639         dcache_enable();
 640 }
 641 #endif  /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 642
 643 #ifdef CONFIG_TFABOOT
 644 enum boot_src __get_boot_src(u32 porsr1)
 645 {
 646         enum boot_src src = BOOT_SOURCE_RESERVED;
 647         u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
 648 #if !defined(CONFIG_NXP_LSCH3_2)
 649         u32 val;
 650 #endif
 651         debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
 652
 653 #if defined(CONFIG_FSL_LSCH3)
 654 #if defined(CONFIG_NXP_LSCH3_2)
 655         switch (rcw_src) {
 656         case RCW_SRC_SDHC1_VAL:
 657                 src = BOOT_SOURCE_SD_MMC;
 658         break;
 659         case RCW_SRC_SDHC2_VAL:
 660                 src = BOOT_SOURCE_SD_MMC2;
 661         break;
 662         case RCW_SRC_I2C1_VAL:
 663                 src = BOOT_SOURCE_I2C1_EXTENDED;
 664         break;
 665         case RCW_SRC_FLEXSPI_NAND2K_VAL:
 666                 src = BOOT_SOURCE_XSPI_NAND;
 667         break;
 668         case RCW_SRC_FLEXSPI_NAND4K_VAL:
 669                 src = BOOT_SOURCE_XSPI_NAND;
 670         break;
 671         case RCW_SRC_RESERVED_1_VAL:
 672                 src = BOOT_SOURCE_RESERVED;
 673         break;
 674         case RCW_SRC_FLEXSPI_NOR_24B:
 675                 src = BOOT_SOURCE_XSPI_NOR;
 676         break;
 677         default:
 678                 src = BOOT_SOURCE_RESERVED;
 679         }
 680 #else
 681         val = rcw_src & RCW_SRC_TYPE_MASK;
 682         if (val == RCW_SRC_NOR_VAL) {
 683                 val = rcw_src & NOR_TYPE_MASK;
 684
 685                 switch (val) {
 686                 case NOR_16B_VAL:
 687                 case NOR_32B_VAL:
 688                         src = BOOT_SOURCE_IFC_NOR;
 689                 break;
 690                 default:
 691                         src = BOOT_SOURCE_RESERVED;
 692                 }
 693         } else {
 694                 /* RCW SRC Serial Flash */
 695                 val = rcw_src & RCW_SRC_SERIAL_MASK;
 696                 switch (val) {
 697                 case RCW_SRC_QSPI_VAL:
 698                 /* RCW SRC Serial NOR (QSPI) */
 699                         src = BOOT_SOURCE_QSPI_NOR;
 700                         break;
 701                 case RCW_SRC_SD_CARD_VAL:
 702                 /* RCW SRC SD Card */
 703                         src = BOOT_SOURCE_SD_MMC;
 704                         break;
 705                 case RCW_SRC_EMMC_VAL:
 706                 /* RCW SRC EMMC */
 707                         src = BOOT_SOURCE_SD_MMC;
 708                         break;
 709                 case RCW_SRC_I2C1_VAL:
 710                 /* RCW SRC I2C1 Extended */
 711                         src = BOOT_SOURCE_I2C1_EXTENDED;
 712                         break;
 713                 default:
 714                         src = BOOT_SOURCE_RESERVED;
 715                 }
 716         }
 717 #endif
 718 #elif defined(CONFIG_FSL_LSCH2)
 719         /* RCW SRC NAND */
 720         val = rcw_src & RCW_SRC_NAND_MASK;
 721         if (val == RCW_SRC_NAND_VAL) {
 722                 val = rcw_src & NAND_RESERVED_MASK;
 723                 if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
 724                         src = BOOT_SOURCE_IFC_NAND;
 725
 726         } else {
 727                 /* RCW SRC NOR */
 728                 val = rcw_src & RCW_SRC_NOR_MASK;
 729                 if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
 730                         src = BOOT_SOURCE_IFC_NOR;
 731                 } else {
 732                         switch (rcw_src) {
 733                         case QSPI_VAL1:
 734                         case QSPI_VAL2:
 735                                 src = BOOT_SOURCE_QSPI_NOR;
 736                                 break;
 737                         case SD_VAL:
 738                                 src = BOOT_SOURCE_SD_MMC;
 739                                 break;
 740                         default:
 741                                 src = BOOT_SOURCE_RESERVED;
 742                         }
 743                 }
 744         }
 745 #endif
 746
 747         if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
 748                 src = BOOT_SOURCE_QSPI_NOR;
 749
 750         debug("%s: src 0x%x\n", __func__, src);
 751         return src;
 752 }
 753
 754 enum boot_src get_boot_src(void)
 755 {
 756         struct pt_regs regs;
 757         u32 porsr1 = 0;
 758
 759 #if defined(CONFIG_FSL_LSCH3)
 760         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 761 #elif defined(CONFIG_FSL_LSCH2)
 762         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 763 #endif
 764
 765         if (current_el() == 2) {
 766                 regs.regs[0] = SIP_SVC_RCW;
 767
 768                 smc_call(&regs);
 769                 if (!regs.regs[0])
 770                         porsr1 = regs.regs[1];
 771         }
 772
 773         if (current_el() == 3 || !porsr1) {
 774 #ifdef CONFIG_FSL_LSCH3
 775                 porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
 776 #elif defined(CONFIG_FSL_LSCH2)
 777                 porsr1 = in_be32(&gur->porsr1);
 778 #endif
 779         }
 780
 781         debug("%s: porsr1 0x%x\n", __func__, porsr1);
 782
 783         return __get_boot_src(porsr1);
 784 }
 785
 786 #ifdef CONFIG_ENV_IS_IN_MMC
 787 int mmc_get_env_dev(void)
 788 {
 789         enum boot_src src = get_boot_src();
 790         int dev = CONFIG_SYS_MMC_ENV_DEV;
 791
 792         switch (src) {
 793         case BOOT_SOURCE_SD_MMC:
 794                 dev = 0;
 795                 break;
 796         case BOOT_SOURCE_SD_MMC2:
 797                 dev = 1;
 798                 break;
 799         default:
 800                 break;
 801         }
 802
 803         return dev;
 804 }
 805 #endif
 806
 807 enum env_location env_get_location(enum env_operation op, int prio)
 808 {
 809         enum boot_src src = get_boot_src();
 810         enum env_location env_loc = ENVL_NOWHERE;
 811
 812         if (prio)
 813                 return ENVL_UNKNOWN;
 814
 815 #ifdef  CONFIG_ENV_IS_NOWHERE
 816         return env_loc;
 817 #endif
 818
 819         switch (src) {
 820         case BOOT_SOURCE_IFC_NOR:
 821                 env_loc = ENVL_FLASH;
 822                 break;
 823         case BOOT_SOURCE_QSPI_NOR:
 824                 /* FALLTHROUGH */
 825         case BOOT_SOURCE_XSPI_NOR:
 826                 env_loc = ENVL_SPI_FLASH;
 827                 break;
 828         case BOOT_SOURCE_IFC_NAND:
 829                 /* FALLTHROUGH */
 830         case BOOT_SOURCE_QSPI_NAND:
 831                 /* FALLTHROUGH */
 832         case BOOT_SOURCE_XSPI_NAND:
 833                 env_loc = ENVL_NAND;
 834                 break;
 835         case BOOT_SOURCE_SD_MMC:
 836                 /* FALLTHROUGH */
 837         case BOOT_SOURCE_SD_MMC2:
 838                 env_loc =  ENVL_MMC;
 839                 break;
 840         case BOOT_SOURCE_I2C1_EXTENDED:
 841                 /* FALLTHROUGH */
 842         default:
 843                 break;
 844         }
 845
 846         return env_loc;
 847 }
 848 #endif  /* CONFIG_TFABOOT */
 849
 850 u32 initiator_type(u32 cluster, int init_id)
 851 {
 852         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 853         u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
 854         u32 type = 0;
 855
 856         type = gur_in32(&gur->tp_ityp[idx]);
 857         if (type & TP_ITYP_AV)
 858                 return type;
 859
 860         return 0;
 861 }
 862
 863 u32 cpu_pos_mask(void)
 864 {
 865         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 866         int i = 0;
 867         u32 cluster, type, mask = 0;
 868
 869         do {
 870                 int j;
 871
 872                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 873                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 874                         type = initiator_type(cluster, j);
 875                         if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
 876                                 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
 877                 }
 878                 i++;
 879         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 880
 881         return mask;
 882 }
 883
 884 u32 cpu_mask(void)
 885 {
 886         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 887         int i = 0, count = 0;
 888         u32 cluster, type, mask = 0;
 889
 890         do {
 891                 int j;
 892
 893                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 894                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 895                         type = initiator_type(cluster, j);
 896                         if (type) {
 897                                 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
 898                                         mask |= 1 << count;
 899                                 count++;
 900                         }
 901                 }
 902                 i++;
 903         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 904
 905         return mask;
 906 }
 907
 908 /*
 909  * Return the number of cores on this SOC.
 910  */
 911 int cpu_numcores(void)
 912 {
 913         return hweight32(cpu_mask());
 914 }
 915
 916 int fsl_qoriq_core_to_cluster(unsigned int core)
 917 {
 918         struct ccsr_gur __iomem *gur =
 919                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 920         int i = 0, count = 0;
 921         u32 cluster;
 922
 923         do {
 924                 int j;
 925
 926                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 927                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 928                         if (initiator_type(cluster, j)) {
 929                                 if (count == core)
 930                                         return i;
 931                                 count++;
 932                         }
 933                 }
 934                 i++;
 935         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 936
 937         return -1;      /* cannot identify the cluster */
 938 }
 939
 940 u32 fsl_qoriq_core_to_type(unsigned int core)
 941 {
 942         struct ccsr_gur __iomem *gur =
 943                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 944         int i = 0, count = 0;
 945         u32 cluster, type;
 946
 947         do {
 948                 int j;
 949
 950                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 951                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 952                         type = initiator_type(cluster, j);
 953                         if (type) {
 954                                 if (count == core)
 955                                         return type;
 956                                 count++;
 957                         }
 958                 }
 959                 i++;
 960         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 961
 962         return -1;      /* cannot identify the cluster */
 963 }
 964
 965 #ifndef CONFIG_FSL_LSCH3
 966 uint get_svr(void)
 967 {
 968         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 969
 970         return gur_in32(&gur->svr);
 971 }
 972 #endif
 973
 974 #ifdef CONFIG_DISPLAY_CPUINFO
 975 int print_cpuinfo(void)
 976 {
 977         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 978         struct sys_info sysinfo;
 979         char buf[32];
 980         unsigned int i, core;
 981         u32 type, rcw, svr = gur_in32(&gur->svr);
 982
 983         puts("SoC: ");
 984
 985         cpu_name(buf);
 986         printf(" %s (0x%x)\n", buf, svr);
 987         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 988         get_sys_info(&sysinfo);
 989         puts("Clock Configuration:");
 990         for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
 991                 if (!(i % 3))
 992                         puts("\n       ");
 993                 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
 994                 printf("CPU%d(%s):%-4s MHz  ", core,
 995                        type == TY_ITYP_VER_A7 ? "A7 " :
 996                        (type == TY_ITYP_VER_A53 ? "A53" :
 997                        (type == TY_ITYP_VER_A57 ? "A57" :
 998                        (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
 999                        strmhz(buf, sysinfo.freq_processor[core]));
1000         }
1001         /* Display platform clock as Bus frequency. */
1002         printf("\n       Bus:      %-4s MHz  ",
1003                strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
1004         printf("DDR:      %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
1005 #ifdef CONFIG_SYS_DPAA_FMAN
1006         printf("  FMAN:     %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
1007 #endif
1008 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
1009         if (soc_has_dp_ddr()) {
1010                 printf("     DP-DDR:   %-4s MT/s",
1011                        strmhz(buf, sysinfo.freq_ddrbus2));
1012         }
1013 #endif
1014         puts("\n");
1015
1016         /*
1017          * Display the RCW, so that no one gets confused as to what RCW
1018          * we're actually using for this boot.
1019          */
1020         puts("Reset Configuration Word (RCW):");
1021         for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
1022                 rcw = gur_in32(&gur->rcwsr[i]);
1023                 if ((i % 4) == 0)
1024                         printf("\n       %08x:", i * 4);
1025                 printf(" %08x", rcw);
1026         }
1027         puts("\n");
1028
1029         return 0;
1030 }
1031 #endif
1032
1033 #ifdef CONFIG_FSL_ESDHC
1034 int cpu_mmc_init(bd_t *bis)
1035 {
1036         return fsl_esdhc_mmc_init(bis);
1037 }
1038 #endif
1039
1040 int cpu_eth_init(bd_t *bis)
1041 {
1042         int error = 0;
1043
1044 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1045         error = fsl_mc_ldpaa_init(bis);
1046 #endif
1047 #ifdef CONFIG_FMAN_ENET
1048         fm_standard_init(bis);
1049 #endif
1050         return error;
1051 }
1052
1053 static inline int check_psci(void)
1054 {
1055         unsigned int psci_ver;
1056
1057         psci_ver = sec_firmware_support_psci_version();
1058         if (psci_ver == PSCI_INVALID_VER)
1059                 return 1;
1060
1061         return 0;
1062 }
1063
1064 static void config_core_prefetch(void)
1065 {
1066         char *buf = NULL;
1067         char buffer[HWCONFIG_BUFFER_SIZE];
1068         const char *prefetch_arg = NULL;
1069         size_t arglen;
1070         unsigned int mask;
1071         struct pt_regs regs;
1072
1073         if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
1074                 buf = buffer;
1075         else
1076                 return;
1077
1078         prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
1079                                          &arglen, buf);
1080
1081         if (prefetch_arg) {
1082                 mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
1083                 if (mask & 0x1) {
1084                         printf("Core0 prefetch can't be disabled\n");
1085                         return;
1086                 }
1087
1088 #define SIP_PREFETCH_DISABLE_64 0xC200FF13
1089                 regs.regs[0] = SIP_PREFETCH_DISABLE_64;
1090                 regs.regs[1] = mask;
1091                 smc_call(&regs);
1092
1093                 if (regs.regs[0])
1094                         printf("Prefetch disable config failed for mask ");
1095                 else
1096                         printf("Prefetch disable config passed for mask ");
1097                 printf("0x%x\n", mask);
1098         }
1099 }
1100
1101 int arch_early_init_r(void)
1102 {
1103 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
1104         u32 svr_dev_id;
1105         /*
1106          * erratum A009635 is valid only for LS2080A SoC and
1107          * its personalitiesi
1108          */
1109         svr_dev_id = get_svr();
1110         if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1111                 erratum_a009635();
1112 #endif
1113 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
1114         erratum_a009942_check_cpo();
1115 #endif
1116         if (check_psci()) {
1117                 debug("PSCI: PSCI does not exist.\n");
1118
1119                 /* if PSCI does not exist, boot secondary cores here */
1120                 if (fsl_layerscape_wake_seconday_cores())
1121                         printf("Did not wake secondary cores\n");
1122         }
1123
1124         config_core_prefetch();
1125
1126 #ifdef CONFIG_SYS_HAS_SERDES
1127         fsl_serdes_init();
1128 #endif
1129 #ifdef CONFIG_SYS_FSL_HAS_RGMII
1130         /* some dpmacs in armv8a based freescale layerscape SOCs can be
1131          * configured via both serdes(sgmii, xfi, xlaui etc) bits and via
1132          * EC*_PMUX(rgmii) bits in RCW.
1133          * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
1134          * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
1135          * Now if a dpmac is enabled by serdes bits then it takes precedence
1136          * over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
1137          * that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
1138          * then the dpmac is SGMII and not RGMII.
1139          *
1140          * Therefore, move the fsl_rgmii_init after fsl_serdes_init. in
1141          * fsl_rgmii_init function of SOC, we will check if the dpmac is enabled
1142          * or not? if it is (fsl_serdes_init has already enabled the dpmac),
1143          * then don't enable it.
1144          */
1145         fsl_rgmii_init();
1146 #endif
1147 #ifdef CONFIG_FMAN_ENET
1148         fman_enet_init();
1149 #endif
1150 #ifdef CONFIG_SYS_DPAA_QBMAN
1151         setup_qbman_portals();
1152 #endif
1153         return 0;
1154 }
1155
1156 int timer_init(void)
1157 {
1158         u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
1159 #ifdef CONFIG_FSL_LSCH3
1160         u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
1161 #endif
1162 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1163         defined(CONFIG_ARCH_LS1028A)
1164         u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
1165         u32 svr_dev_id;
1166 #endif
1167 #ifdef COUNTER_FREQUENCY_REAL
1168         unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
1169
1170         /* Update with accurate clock frequency */
1171         if (current_el() == 3)
1172                 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
1173 #endif
1174
1175 #ifdef CONFIG_FSL_LSCH3
1176         /* Enable timebase for all clusters.
1177          * It is safe to do so even some clusters are not enabled.
1178          */
1179         out_le32(cltbenr, 0xf);
1180 #endif
1181
1182 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
1183         defined(CONFIG_ARCH_LS1028A)
1184         /*
1185          * In certain Layerscape SoCs, the clock for each core's
1186          * has an enable bit in the PMU Physical Core Time Base Enable
1187          * Register (PCTBENR), which allows the watchdog to operate.
1188          */
1189         setbits_le32(pctbenr, 0xff);
1190         /*
1191          * For LS2080A SoC and its personalities, timer controller
1192          * offset is different
1193          */
1194         svr_dev_id = get_svr();
1195         if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1196                 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
1197
1198 #endif
1199
1200         /* Enable clock for timer
1201          * This is a global setting.
1202          */
1203         out_le32(cntcr, 0x1);
1204
1205         return 0;
1206 }
1207
1208 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
1209
1210 void __efi_runtime reset_cpu(ulong addr)
1211 {
1212         u32 val;
1213
1214 #ifdef CONFIG_ARCH_LX2160A
1215         val = in_le32(rstcr);
1216         val |= 0x01;
1217         out_le32(rstcr, val);
1218 #else
1219         /* Raise RESET_REQ_B */
1220         val = scfg_in32(rstcr);
1221         val |= 0x02;
1222         scfg_out32(rstcr, val);
1223 #endif
1224 }
1225
1226 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_PSCI_RESET)
1227
1228 void __efi_runtime EFIAPI efi_reset_system(
1229                        enum efi_reset_type reset_type,
1230                        efi_status_t reset_status,
1231                        unsigned long data_size, void *reset_data)
1232 {
1233         switch (reset_type) {
1234         case EFI_RESET_COLD:
1235         case EFI_RESET_WARM:
1236         case EFI_RESET_PLATFORM_SPECIFIC:
1237                 reset_cpu(0);
1238                 break;
1239         case EFI_RESET_SHUTDOWN:
1240                 /* Nothing we can do */
1241                 break;
1242         }
1243
1244         while (1) { }
1245 }
1246
1247 efi_status_t efi_reset_system_init(void)
1248 {
1249         return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
1250 }
1251
1252 #endif
1253
1254 /*
1255  * Calculate reserved memory with given memory bank
1256  * Return aligned memory size on success
1257  * Return (ram_size + needed size) for failure
1258  */
1259 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
1260 {
1261         phys_size_t ram_top = ram_size;
1262
1263 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1264         ram_top = mc_get_dram_block_size();
1265         if (ram_top > ram_size)
1266                 return ram_size + ram_top;
1267
1268         ram_top = ram_size - ram_top;
1269         /* The start address of MC reserved memory needs to be aligned. */
1270         ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
1271 #endif
1272
1273         return ram_size - ram_top;
1274 }
1275
1276 phys_size_t get_effective_memsize(void)
1277 {
1278         phys_size_t ea_size, rem = 0;
1279
1280         /*
1281          * For ARMv8 SoCs, DDR memory is split into two or three regions. The
1282          * first region is 2GB space at 0x8000_0000. Secure memory needs to
1283          * allocated from first region. If the memory extends to  the second
1284          * region (or the third region if applicable), Management Complex (MC)
1285          * memory should be put into the highest region, i.e. the end of DDR
1286          * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
1287          * U-Boot doesn't relocate itself into higher address. Should DDR be
1288          * configured to skip the first region, this function needs to be
1289          * adjusted.
1290          */
1291         if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
1292                 ea_size = CONFIG_MAX_MEM_MAPPED;
1293                 rem = gd->ram_size - ea_size;
1294         } else {
1295                 ea_size = gd->ram_size;
1296         }
1297
1298 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1299         /* Check if we have enough space for secure memory */
1300         if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
1301                 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1302         else
1303                 printf("Error: No enough space for secure memory.\n");
1304 #endif
1305         /* Check if we have enough memory for MC */
1306         if (rem < board_reserve_ram_top(rem)) {
1307                 /* Not enough memory in high region to reserve */
1308                 if (ea_size > board_reserve_ram_top(ea_size))
1309                         ea_size -= board_reserve_ram_top(ea_size);
1310                 else
1311                         printf("Error: No enough space for reserved memory.\n");
1312         }
1313
1314         return ea_size;
1315 }
1316
1317 #ifdef CONFIG_TFABOOT
1318 phys_size_t tfa_get_dram_size(void)
1319 {
1320         struct pt_regs regs;
1321         phys_size_t dram_size = 0;
1322
1323         regs.regs[0] = SMC_DRAM_BANK_INFO;
1324         regs.regs[1] = -1;
1325
1326         smc_call(&regs);
1327         if (regs.regs[0])
1328                 return 0;
1329
1330         dram_size = regs.regs[1];
1331         return dram_size;
1332 }
1333
1334 static int tfa_dram_init_banksize(void)
1335 {
1336         int i = 0, ret = 0;
1337         struct pt_regs regs;
1338         phys_size_t dram_size = tfa_get_dram_size();
1339
1340         debug("dram_size %llx\n", dram_size);
1341
1342         if (!dram_size)
1343                 return -EINVAL;
1344
1345         do {
1346                 regs.regs[0] = SMC_DRAM_BANK_INFO;
1347                 regs.regs[1] = i;
1348
1349                 smc_call(&regs);
1350                 if (regs.regs[0]) {
1351                         ret = -EINVAL;
1352                         break;
1353                 }
1354
1355                 debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
1356                       regs.regs[2]);
1357                 gd->bd->bi_dram[i].start = regs.regs[1];
1358                 gd->bd->bi_dram[i].size = regs.regs[2];
1359
1360                 dram_size -= gd->bd->bi_dram[i].size;
1361
1362                 i++;
1363         } while (dram_size);
1364
1365         if (i > 0)
1366                 ret = 0;
1367
1368 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1369         /* Assign memory for MC */
1370 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1371         if (gd->bd->bi_dram[2].size >=
1372             board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1373                 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1374                             gd->bd->bi_dram[2].size -
1375                             board_reserve_ram_top(gd->bd->bi_dram[2].size);
1376         } else
1377 #endif
1378         {
1379                 if (gd->bd->bi_dram[1].size >=
1380                     board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1381                         gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1382                                 gd->bd->bi_dram[1].size -
1383                                 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1384                 } else if (gd->bd->bi_dram[0].size >
1385                            board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1386                         gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1387                                 gd->bd->bi_dram[0].size -
1388                                 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1389                 }
1390         }
1391 #endif  /* CONFIG_FSL_MC_ENET */
1392
1393         return ret;
1394 }
1395 #endif
1396
1397 int dram_init_banksize(void)
1398 {
1399 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1400         phys_size_t dp_ddr_size;
1401 #endif
1402
1403 #ifdef CONFIG_TFABOOT
1404         if (!tfa_dram_init_banksize())
1405                 return 0;
1406 #endif
1407         /*
1408          * gd->ram_size has the total size of DDR memory, less reserved secure
1409          * memory. The DDR extends from low region to high region(s) presuming
1410          * no hole is created with DDR configuration. gd->arch.secure_ram tracks
1411          * the location of secure memory. gd->arch.resv_ram tracks the location
1412          * of reserved memory for Management Complex (MC). Because gd->ram_size
1413          * is reduced by this function if secure memory is reserved, checking
1414          * gd->arch.secure_ram should be done to avoid running it repeatedly.
1415          */
1416
1417 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1418         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
1419                 debug("No need to run again, skip %s\n", __func__);
1420
1421                 return 0;
1422         }
1423 #endif
1424
1425         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
1426         if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
1427                 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
1428                 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
1429                 gd->bd->bi_dram[1].size = gd->ram_size -
1430                                           CONFIG_SYS_DDR_BLOCK1_SIZE;
1431 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1432                 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
1433                         gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
1434                         gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
1435                                                   CONFIG_SYS_DDR_BLOCK2_SIZE;
1436                         gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
1437                 }
1438 #endif
1439         } else {
1440                 gd->bd->bi_dram[0].size = gd->ram_size;
1441         }
1442 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1443         if (gd->bd->bi_dram[0].size >
1444                                 CONFIG_SYS_MEM_RESERVE_SECURE) {
1445                 gd->bd->bi_dram[0].size -=
1446                                 CONFIG_SYS_MEM_RESERVE_SECURE;
1447                 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
1448                                       gd->bd->bi_dram[0].size;
1449                 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
1450                 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1451         }
1452 #endif  /* CONFIG_SYS_MEM_RESERVE_SECURE */
1453
1454 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1455         /* Assign memory for MC */
1456 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1457         if (gd->bd->bi_dram[2].size >=
1458             board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1459                 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1460                             gd->bd->bi_dram[2].size -
1461                             board_reserve_ram_top(gd->bd->bi_dram[2].size);
1462         } else
1463 #endif
1464         {
1465                 if (gd->bd->bi_dram[1].size >=
1466                     board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1467                         gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1468                                 gd->bd->bi_dram[1].size -
1469                                 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1470                 } else if (gd->bd->bi_dram[0].size >
1471                            board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1472                         gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1473                                 gd->bd->bi_dram[0].size -
1474                                 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1475                 }
1476         }
1477 #endif  /* CONFIG_FSL_MC_ENET */
1478
1479 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1480 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1481 #error "This SoC shouldn't have DP DDR"
1482 #endif
1483         if (soc_has_dp_ddr()) {
1484                 /* initialize DP-DDR here */
1485                 puts("DP-DDR:  ");
1486                 /*
1487                  * DDR controller use 0 as the base address for binding.
1488                  * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
1489                  */
1490                 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
1491                                           CONFIG_DP_DDR_CTRL,
1492                                           CONFIG_DP_DDR_NUM_CTRLS,
1493                                           CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
1494                                           NULL, NULL, NULL);
1495                 if (dp_ddr_size) {
1496                         gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
1497                         gd->bd->bi_dram[2].size = dp_ddr_size;
1498                 } else {
1499                         puts("Not detected");
1500                 }
1501         }
1502 #endif
1503
1504 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1505         debug("%s is called. gd->ram_size is reduced to %lu\n",
1506               __func__, (ulong)gd->ram_size);
1507 #endif
1508
1509         return 0;
1510 }
1511
1512 #if CONFIG_IS_ENABLED(EFI_LOADER)
1513 void efi_add_known_memory(void)
1514 {
1515         int i;
1516         phys_addr_t ram_start, start;
1517         phys_size_t ram_size;
1518         u64 pages;
1519
1520         /* Add RAM */
1521         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
1522 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1523 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1524 #error "This SoC shouldn't have DP DDR"
1525 #endif
1526                 if (i == 2)
1527                         continue;       /* skip DP-DDR */
1528 #endif
1529                 ram_start = gd->bd->bi_dram[i].start;
1530                 ram_size = gd->bd->bi_dram[i].size;
1531 #ifdef CONFIG_RESV_RAM
1532                 if (gd->arch.resv_ram >= ram_start &&
1533                     gd->arch.resv_ram < ram_start + ram_size)
1534                         ram_size = gd->arch.resv_ram - ram_start;
1535 #endif
1536                 start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
1537                 pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
1538
1539                 efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY,
1540                                    false);
1541         }
1542 }
1543 #endif
1544
1545 /*
1546  * Before DDR size is known, early MMU table have DDR mapped as device memory
1547  * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
1548  * needs to be set for these mappings.
1549  * If a special case configures DDR with holes in the mapping, the holes need
1550  * to be marked as invalid. This is not implemented in this function.
1551  */
1552 void update_early_mmu_table(void)
1553 {
1554         if (!gd->arch.tlb_addr)
1555                 return;
1556
1557         if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
1558                 mmu_change_region_attr(
1559                                         CONFIG_SYS_SDRAM_BASE,
1560                                         gd->ram_size,
1561                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1562                                         PTE_BLOCK_OUTER_SHARE           |
1563                                         PTE_BLOCK_NS                    |
1564                                         PTE_TYPE_VALID);
1565         } else {
1566                 mmu_change_region_attr(
1567                                         CONFIG_SYS_SDRAM_BASE,
1568                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
1569                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1570                                         PTE_BLOCK_OUTER_SHARE           |
1571                                         PTE_BLOCK_NS                    |
1572                                         PTE_TYPE_VALID);
1573 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1574 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
1575 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
1576 #endif
1577                 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
1578                     CONFIG_SYS_DDR_BLOCK2_SIZE) {
1579                         mmu_change_region_attr(
1580                                         CONFIG_SYS_DDR_BLOCK2_BASE,
1581                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
1582                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1583                                         PTE_BLOCK_OUTER_SHARE           |
1584                                         PTE_BLOCK_NS                    |
1585                                         PTE_TYPE_VALID);
1586                         mmu_change_region_attr(
1587                                         CONFIG_SYS_DDR_BLOCK3_BASE,
1588                                         gd->ram_size -
1589                                         CONFIG_SYS_DDR_BLOCK1_SIZE -
1590                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
1591                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1592                                         PTE_BLOCK_OUTER_SHARE           |
1593                                         PTE_BLOCK_NS                    |
1594                                         PTE_TYPE_VALID);
1595                 } else
1596 #endif
1597                 {
1598                         mmu_change_region_attr(
1599                                         CONFIG_SYS_DDR_BLOCK2_BASE,
1600                                         gd->ram_size -
1601                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
1602                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1603                                         PTE_BLOCK_OUTER_SHARE           |
1604                                         PTE_BLOCK_NS                    |
1605                                         PTE_TYPE_VALID);
1606                 }
1607         }
1608 }
1609
1610 __weak int dram_init(void)
1611 {
1612         fsl_initdram();
1613 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
1614         defined(CONFIG_SPL_BUILD)
1615         /* This will break-before-make MMU for DDR */
1616         update_early_mmu_table();
1617 #endif
1618
1619         return 0;
1620 }