arch/arm/cpu/armv8/fsl-layerscape/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2017 NXP
   4  * Copyright 2014-2015 Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <common.h>
   8 #include <fsl_ddr_sdram.h>
   9 #include <asm/io.h>
  10 #include <linux/errno.h>
  11 #include <asm/system.h>
  12 #include <fm_eth.h>
  13 #include <asm/armv8/mmu.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/fsl_serdes.h>
  16 #include <asm/arch/soc.h>
  17 #include <asm/arch/cpu.h>
  18 #include <asm/arch/speed.h>
  19 #include <fsl_immap.h>
  20 #include <asm/arch/mp.h>
  21 #include <efi_loader.h>
  22 #include <fsl-mc/fsl_mc.h>
  23 #ifdef CONFIG_FSL_ESDHC
  24 #include <fsl_esdhc.h>
  25 #endif
  26 #include <asm/armv8/sec_firmware.h>
  27 #ifdef CONFIG_SYS_FSL_DDR
  28 #include <fsl_ddr.h>
  29 #endif
  30 #include <asm/arch/clock.h>
  31 #include <hwconfig.h>
  32 #include <fsl_qbman.h>
  33
  34 #ifdef CONFIG_TFABOOT
  35 #include <environment.h>
  36 #ifdef CONFIG_CHAIN_OF_TRUST
  37 #include <fsl_validate.h>
  38 #endif
  39 #endif
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 static struct cpu_type cpu_type_list[] = {
  44         CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
  45         CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
  46         CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
  47         CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
  48         CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
  49         CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
  50         CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
  51         CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
  52         CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
  53         CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
  54         CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
  55         CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
  56         CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
  57         CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
  58         CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
  59         CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
  60         CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
  61         CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
  62         CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
  63 };
  64
  65 #define EARLY_PGTABLE_SIZE 0x5000
  66 static struct mm_region early_map[] = {
  67 #ifdef CONFIG_FSL_LSCH3
  68         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
  69           CONFIG_SYS_FSL_CCSR_SIZE,
  70           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  71           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
  72         },
  73         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  74           SYS_FSL_OCRAM_SPACE_SIZE,
  75           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
  76         },
  77         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
  78           CONFIG_SYS_FSL_QSPI_SIZE1,
  79           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
  80 #ifdef CONFIG_FSL_IFC
  81         /* For IFC Region #1, only the first 4MB is cache-enabled */
  82         { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
  83           CONFIG_SYS_FSL_IFC_SIZE1_1,
  84           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
  85         },
  86         { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
  87           CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
  88           CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
  89           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
  90         },
  91         { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
  92           CONFIG_SYS_FSL_IFC_SIZE1,
  93           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
  94         },
  95 #endif
  96         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
  97           CONFIG_SYS_FSL_DRAM_SIZE1,
  98 #if defined(CONFIG_TFABOOT) || \
  99         (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 100           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 101 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
 102           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 103 #endif
 104           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 105         },
 106 #ifdef CONFIG_FSL_IFC
 107         /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
 108         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 109           CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
 110           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 111         },
 112 #endif
 113         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 114           CONFIG_SYS_FSL_DCSR_SIZE,
 115           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 116           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 117         },
 118         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 119           CONFIG_SYS_FSL_DRAM_SIZE2,
 120           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 121           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 122         },
 123 #elif defined(CONFIG_FSL_LSCH2)
 124         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 125           CONFIG_SYS_FSL_CCSR_SIZE,
 126           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 127           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 128         },
 129         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 130           SYS_FSL_OCRAM_SPACE_SIZE,
 131           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 132         },
 133         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 134           CONFIG_SYS_FSL_DCSR_SIZE,
 135           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 136           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 137         },
 138         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 139           CONFIG_SYS_FSL_QSPI_SIZE,
 140           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 141         },
 142 #ifdef CONFIG_FSL_IFC
 143         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 144           CONFIG_SYS_FSL_IFC_SIZE,
 145           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 146         },
 147 #endif
 148         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 149           CONFIG_SYS_FSL_DRAM_SIZE1,
 150 #if defined(CONFIG_TFABOOT) || \
 151         (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 152           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 153 #else   /* Start with nGnRnE and PXN and UXN to prevent speculative access */
 154           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 155 #endif
 156           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 157         },
 158         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 159           CONFIG_SYS_FSL_DRAM_SIZE2,
 160           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
 161           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 162         },
 163 #endif
 164         {},     /* list terminator */
 165 };
 166
 167 static struct mm_region final_map[] = {
 168 #ifdef CONFIG_FSL_LSCH3
 169         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 170           CONFIG_SYS_FSL_CCSR_SIZE,
 171           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 172           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 173         },
 174         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 175           SYS_FSL_OCRAM_SPACE_SIZE,
 176           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 177         },
 178         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 179           CONFIG_SYS_FSL_DRAM_SIZE1,
 180           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 181           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 182         },
 183         { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
 184           CONFIG_SYS_FSL_QSPI_SIZE1,
 185           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 186           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 187         },
 188         { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
 189           CONFIG_SYS_FSL_QSPI_SIZE2,
 190           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 191           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 192         },
 193 #ifdef CONFIG_FSL_IFC
 194         { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
 195           CONFIG_SYS_FSL_IFC_SIZE2,
 196           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 197           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 198         },
 199 #endif
 200         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 201           CONFIG_SYS_FSL_DCSR_SIZE,
 202           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 203           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 204         },
 205         { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
 206           CONFIG_SYS_FSL_MC_SIZE,
 207           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 208           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 209         },
 210         { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
 211           CONFIG_SYS_FSL_NI_SIZE,
 212           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 213           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 214         },
 215         /* For QBMAN portal, only the first 64MB is cache-enabled */
 216         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 217           CONFIG_SYS_FSL_QBMAN_SIZE_1,
 218           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 219           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
 220         },
 221         { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 222           CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
 223           CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
 224           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 225           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 226         },
 227         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 228           CONFIG_SYS_PCIE1_PHYS_SIZE,
 229           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 230           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 231         },
 232         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 233           CONFIG_SYS_PCIE2_PHYS_SIZE,
 234           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 235           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 236         },
 237         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 238           CONFIG_SYS_PCIE3_PHYS_SIZE,
 239           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 240           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 241         },
 242 #ifdef CONFIG_ARCH_LS2080A
 243         { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
 244           CONFIG_SYS_PCIE4_PHYS_SIZE,
 245           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 246           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 247         },
 248 #endif
 249         { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
 250           CONFIG_SYS_FSL_WRIOP1_SIZE,
 251           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 252           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 253         },
 254         { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
 255           CONFIG_SYS_FSL_AIOP1_SIZE,
 256           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 257           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 258         },
 259         { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
 260           CONFIG_SYS_FSL_PEBUF_SIZE,
 261           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 262           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 263         },
 264         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 265           CONFIG_SYS_FSL_DRAM_SIZE2,
 266           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 267           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 268         },
 269 #elif defined(CONFIG_FSL_LSCH2)
 270         { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
 271           CONFIG_SYS_FSL_BOOTROM_SIZE,
 272           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 273           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 274         },
 275         { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
 276           CONFIG_SYS_FSL_CCSR_SIZE,
 277           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 278           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 279         },
 280         { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
 281           SYS_FSL_OCRAM_SPACE_SIZE,
 282           PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
 283         },
 284         { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
 285           CONFIG_SYS_FSL_DCSR_SIZE,
 286           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 287           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 288         },
 289         { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
 290           CONFIG_SYS_FSL_QSPI_SIZE,
 291           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 292           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 293         },
 294 #ifdef CONFIG_FSL_IFC
 295         { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
 296           CONFIG_SYS_FSL_IFC_SIZE,
 297           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
 298         },
 299 #endif
 300         { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
 301           CONFIG_SYS_FSL_DRAM_SIZE1,
 302           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 303           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 304         },
 305         { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
 306           CONFIG_SYS_FSL_QBMAN_SIZE,
 307           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 308           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 309         },
 310         { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
 311           CONFIG_SYS_FSL_DRAM_SIZE2,
 312           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 313           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 314         },
 315         { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
 316           CONFIG_SYS_PCIE1_PHYS_SIZE,
 317           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 318           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 319         },
 320         { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
 321           CONFIG_SYS_PCIE2_PHYS_SIZE,
 322           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 323           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 324         },
 325         { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
 326           CONFIG_SYS_PCIE3_PHYS_SIZE,
 327           PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
 328           PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
 329         },
 330         { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
 331           CONFIG_SYS_FSL_DRAM_SIZE3,
 332           PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 333           PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
 334         },
 335 #endif
 336 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 337         {},     /* space holder for secure mem */
 338 #endif
 339         {},
 340 };
 341
 342 struct mm_region *mem_map = early_map;
 343
 344 void cpu_name(char *name)
 345 {
 346         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 347         unsigned int i, svr, ver;
 348
 349         svr = gur_in32(&gur->svr);
 350         ver = SVR_SOC_VER(svr);
 351
 352         for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
 353                 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
 354                         strcpy(name, cpu_type_list[i].name);
 355
 356                         if (IS_E_PROCESSOR(svr))
 357                                 strcat(name, "E");
 358
 359                         sprintf(name + strlen(name), " Rev%d.%d",
 360                                 SVR_MAJ(svr), SVR_MIN(svr));
 361                         break;
 362                 }
 363
 364         if (i == ARRAY_SIZE(cpu_type_list))
 365                 strcpy(name, "unknown");
 366 }
 367
 368 #ifndef CONFIG_SYS_DCACHE_OFF
 369 /*
 370  * To start MMU before DDR is available, we create MMU table in SRAM.
 371  * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
 372  * levels of translation tables here to cover 40-bit address space.
 373  * We use 4KB granule size, with 40 bits physical address, T0SZ=24
 374  * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
 375  * Note, the debug print in cache_v8.c is not usable for debugging
 376  * these early MMU tables because UART is not yet available.
 377  */
 378 static inline void early_mmu_setup(void)
 379 {
 380         unsigned int el = current_el();
 381
 382         /* global data is already setup, no allocation yet */
 383         if (el == 3)
 384                 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
 385         else
 386                 gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
 387         gd->arch.tlb_fillptr = gd->arch.tlb_addr;
 388         gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
 389
 390         /* Create early page tables */
 391         setup_pgtables();
 392
 393         /* point TTBR to the new table */
 394         set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
 395                           get_tcr(el, NULL, NULL) &
 396                           ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
 397                           MEMORY_ATTRIBUTES);
 398
 399         set_sctlr(get_sctlr() | CR_M);
 400 }
 401
 402 static void fix_pcie_mmu_map(void)
 403 {
 404 #ifdef CONFIG_ARCH_LS2080A
 405         unsigned int i;
 406         u32 svr, ver;
 407         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 408
 409         svr = gur_in32(&gur->svr);
 410         ver = SVR_SOC_VER(svr);
 411
 412         /* Fix PCIE base and size for LS2088A */
 413         if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
 414             (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
 415             (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
 416                 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
 417                         switch (final_map[i].phys) {
 418                         case CONFIG_SYS_PCIE1_PHYS_ADDR:
 419                                 final_map[i].phys = 0x2000000000ULL;
 420                                 final_map[i].virt = 0x2000000000ULL;
 421                                 final_map[i].size = 0x800000000ULL;
 422                                 break;
 423                         case CONFIG_SYS_PCIE2_PHYS_ADDR:
 424                                 final_map[i].phys = 0x2800000000ULL;
 425                                 final_map[i].virt = 0x2800000000ULL;
 426                                 final_map[i].size = 0x800000000ULL;
 427                                 break;
 428                         case CONFIG_SYS_PCIE3_PHYS_ADDR:
 429                                 final_map[i].phys = 0x3000000000ULL;
 430                                 final_map[i].virt = 0x3000000000ULL;
 431                                 final_map[i].size = 0x800000000ULL;
 432                                 break;
 433                         case CONFIG_SYS_PCIE4_PHYS_ADDR:
 434                                 final_map[i].phys = 0x3800000000ULL;
 435                                 final_map[i].virt = 0x3800000000ULL;
 436                                 final_map[i].size = 0x800000000ULL;
 437                                 break;
 438                         default:
 439                                 break;
 440                         }
 441                 }
 442         }
 443 #endif
 444 }
 445
 446 /*
 447  * The final tables look similar to early tables, but different in detail.
 448  * These tables are in DRAM. Sub tables are added to enable cache for
 449  * QBMan and OCRAM.
 450  *
 451  * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
 452  * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
 453  */
 454 static inline void final_mmu_setup(void)
 455 {
 456         u64 tlb_addr_save = gd->arch.tlb_addr;
 457         unsigned int el = current_el();
 458         int index;
 459
 460         /* fix the final_map before filling in the block entries */
 461         fix_pcie_mmu_map();
 462
 463         mem_map = final_map;
 464
 465         /* Update mapping for DDR to actual size */
 466         for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
 467                 /*
 468                  * Find the entry for DDR mapping and update the address and
 469                  * size. Zero-sized mapping will be skipped when creating MMU
 470                  * table.
 471                  */
 472                 switch (final_map[index].virt) {
 473                 case CONFIG_SYS_FSL_DRAM_BASE1:
 474                         final_map[index].virt = gd->bd->bi_dram[0].start;
 475                         final_map[index].phys = gd->bd->bi_dram[0].start;
 476                         final_map[index].size = gd->bd->bi_dram[0].size;
 477                         break;
 478 #ifdef CONFIG_SYS_FSL_DRAM_BASE2
 479                 case CONFIG_SYS_FSL_DRAM_BASE2:
 480 #if (CONFIG_NR_DRAM_BANKS >= 2)
 481                         final_map[index].virt = gd->bd->bi_dram[1].start;
 482                         final_map[index].phys = gd->bd->bi_dram[1].start;
 483                         final_map[index].size = gd->bd->bi_dram[1].size;
 484 #else
 485                         final_map[index].size = 0;
 486 #endif
 487                 break;
 488 #endif
 489 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 490                 case CONFIG_SYS_FSL_DRAM_BASE3:
 491 #if (CONFIG_NR_DRAM_BANKS >= 3)
 492                         final_map[index].virt = gd->bd->bi_dram[2].start;
 493                         final_map[index].phys = gd->bd->bi_dram[2].start;
 494                         final_map[index].size = gd->bd->bi_dram[2].size;
 495 #else
 496                         final_map[index].size = 0;
 497 #endif
 498                 break;
 499 #endif
 500                 default:
 501                         break;
 502                 }
 503         }
 504
 505 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 506         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 507                 if (el == 3) {
 508                         /*
 509                          * Only use gd->arch.secure_ram if the address is
 510                          * recalculated. Align to 4KB for MMU table.
 511                          */
 512                         /* put page tables in secure ram */
 513                         index = ARRAY_SIZE(final_map) - 2;
 514                         gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
 515                         final_map[index].virt = gd->arch.secure_ram & ~0x3;
 516                         final_map[index].phys = final_map[index].virt;
 517                         final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
 518                         final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
 519                         gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
 520                         tlb_addr_save = gd->arch.tlb_addr;
 521                 } else {
 522                         /* Use allocated (board_f.c) memory for TLB */
 523                         tlb_addr_save = gd->arch.tlb_allocated;
 524                         gd->arch.tlb_addr = tlb_addr_save;
 525                 }
 526         }
 527 #endif
 528
 529         /* Reset the fill ptr */
 530         gd->arch.tlb_fillptr = tlb_addr_save;
 531
 532         /* Create normal system page tables */
 533         setup_pgtables();
 534
 535         /* Create emergency page tables */
 536         gd->arch.tlb_addr = gd->arch.tlb_fillptr;
 537         gd->arch.tlb_emerg = gd->arch.tlb_addr;
 538         setup_pgtables();
 539         gd->arch.tlb_addr = tlb_addr_save;
 540
 541         /* Disable cache and MMU */
 542         dcache_disable();       /* TLBs are invalidated */
 543         invalidate_icache_all();
 544
 545         /* point TTBR to the new table */
 546         set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
 547                           MEMORY_ATTRIBUTES);
 548
 549         set_sctlr(get_sctlr() | CR_M);
 550 }
 551
 552 u64 get_page_table_size(void)
 553 {
 554         return 0x10000;
 555 }
 556
 557 int arch_cpu_init(void)
 558 {
 559         /*
 560          * This function is called before U-Boot relocates itself to speed up
 561          * on system running. It is not necessary to run if performance is not
 562          * critical. Skip if MMU is already enabled by SPL or other means.
 563          */
 564         if (get_sctlr() & CR_M)
 565                 return 0;
 566
 567         icache_enable();
 568         __asm_invalidate_dcache_all();
 569         __asm_invalidate_tlb_all();
 570         early_mmu_setup();
 571         set_sctlr(get_sctlr() | CR_C);
 572         return 0;
 573 }
 574
 575 void mmu_setup(void)
 576 {
 577         final_mmu_setup();
 578 }
 579
 580 /*
 581  * This function is called from common/board_r.c.
 582  * It recreates MMU table in main memory.
 583  */
 584 void enable_caches(void)
 585 {
 586         mmu_setup();
 587         __asm_invalidate_tlb_all();
 588         icache_enable();
 589         dcache_enable();
 590 }
 591 #endif  /* CONFIG_SYS_DCACHE_OFF */
 592
 593 #ifdef CONFIG_TFABOOT
 594 enum boot_src __get_boot_src(u32 porsr1)
 595 {
 596         enum boot_src src = BOOT_SOURCE_RESERVED;
 597         u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
 598 #if !defined(CONFIG_FSL_LSCH3_2)
 599         u32 val;
 600 #endif
 601         debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
 602
 603 #if defined(CONFIG_FSL_LSCH3)
 604 #if defined(CONFIG_FSL_LSCH3_2)
 605         switch (rcw_src) {
 606         case RCW_SRC_SDHC1_VAL:
 607                 src = BOOT_SOURCE_SD_MMC;
 608         break;
 609         case RCW_SRC_SDHC2_VAL:
 610                 src = BOOT_SOURCE_SD_MMC2;
 611         break;
 612         case RCW_SRC_I2C1_VAL:
 613                 src = BOOT_SOURCE_I2C1_EXTENDED;
 614         break;
 615         case RCW_SRC_FLEXSPI_NAND2K_VAL:
 616                 src = BOOT_SOURCE_XSPI_NAND;
 617         break;
 618         case RCW_SRC_FLEXSPI_NAND4K_VAL:
 619                 src = BOOT_SOURCE_XSPI_NAND;
 620         break;
 621         case RCW_SRC_RESERVED_1_VAL:
 622                 src = BOOT_SOURCE_RESERVED;
 623         break;
 624         case RCW_SRC_FLEXSPI_NOR_24B:
 625                 src = BOOT_SOURCE_XSPI_NOR;
 626         break;
 627         default:
 628                 src = BOOT_SOURCE_RESERVED;
 629         }
 630 #else
 631         val = rcw_src & RCW_SRC_TYPE_MASK;
 632         if (val == RCW_SRC_NOR_VAL) {
 633                 val = rcw_src & NOR_TYPE_MASK;
 634
 635                 switch (val) {
 636                 case NOR_16B_VAL:
 637                 case NOR_32B_VAL:
 638                         src = BOOT_SOURCE_IFC_NOR;
 639                 break;
 640                 default:
 641                         src = BOOT_SOURCE_RESERVED;
 642                 }
 643         } else {
 644                 /* RCW SRC Serial Flash */
 645                 val = rcw_src & RCW_SRC_SERIAL_MASK;
 646                 switch (val) {
 647                 case RCW_SRC_QSPI_VAL:
 648                 /* RCW SRC Serial NOR (QSPI) */
 649                         src = BOOT_SOURCE_QSPI_NOR;
 650                         break;
 651                 case RCW_SRC_SD_CARD_VAL:
 652                 /* RCW SRC SD Card */
 653                         src = BOOT_SOURCE_SD_MMC;
 654                         break;
 655                 case RCW_SRC_EMMC_VAL:
 656                 /* RCW SRC EMMC */
 657                         src = BOOT_SOURCE_SD_MMC2;
 658                         break;
 659                 case RCW_SRC_I2C1_VAL:
 660                 /* RCW SRC I2C1 Extended */
 661                         src = BOOT_SOURCE_I2C1_EXTENDED;
 662                         break;
 663                 default:
 664                         src = BOOT_SOURCE_RESERVED;
 665                 }
 666         }
 667 #endif
 668 #elif defined(CONFIG_FSL_LSCH2)
 669         /* RCW SRC NAND */
 670         val = rcw_src & RCW_SRC_NAND_MASK;
 671         if (val == RCW_SRC_NAND_VAL) {
 672                 val = rcw_src & NAND_RESERVED_MASK;
 673                 if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
 674                         src = BOOT_SOURCE_IFC_NAND;
 675
 676         } else {
 677                 /* RCW SRC NOR */
 678                 val = rcw_src & RCW_SRC_NOR_MASK;
 679                 if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
 680                         src = BOOT_SOURCE_IFC_NOR;
 681                 } else {
 682                         switch (rcw_src) {
 683                         case QSPI_VAL1:
 684                         case QSPI_VAL2:
 685                                 src = BOOT_SOURCE_QSPI_NOR;
 686                                 break;
 687                         case SD_VAL:
 688                                 src = BOOT_SOURCE_SD_MMC;
 689                                 break;
 690                         default:
 691                                 src = BOOT_SOURCE_RESERVED;
 692                         }
 693                 }
 694         }
 695 #endif
 696         debug("%s: src 0x%x\n", __func__, src);
 697         return src;
 698 }
 699
 700 enum boot_src get_boot_src(void)
 701 {
 702         u32 porsr1;
 703
 704 #if defined(CONFIG_FSL_LSCH3)
 705         u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
 706
 707         porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
 708 #elif defined(CONFIG_FSL_LSCH2)
 709         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 710
 711         porsr1 = in_be32(&gur->porsr1);
 712 #endif
 713         debug("%s: porsr1 0x%x\n", __func__, porsr1);
 714
 715         return __get_boot_src(porsr1);
 716 }
 717
 718 #ifdef CONFIG_ENV_IS_IN_MMC
 719 int mmc_get_env_dev(void)
 720 {
 721         enum boot_src src = get_boot_src();
 722         int dev = CONFIG_SYS_MMC_ENV_DEV;
 723
 724         switch (src) {
 725         case BOOT_SOURCE_SD_MMC:
 726                 dev = 0;
 727                 break;
 728         case BOOT_SOURCE_SD_MMC2:
 729                 dev = 1;
 730                 break;
 731         default:
 732                 break;
 733         }
 734
 735         return dev;
 736 }
 737 #endif
 738
 739 enum env_location env_get_location(enum env_operation op, int prio)
 740 {
 741         enum boot_src src = get_boot_src();
 742         enum env_location env_loc = ENVL_NOWHERE;
 743
 744         if (prio)
 745                 return ENVL_UNKNOWN;
 746
 747 #ifdef CONFIG_CHAIN_OF_TRUST
 748         /* Check Boot Mode
 749          * If Boot Mode is Secure, return ENVL_NOWHERE
 750          */
 751         if (fsl_check_boot_mode_secure() == 1)
 752                 goto done;
 753 #endif
 754
 755         switch (src) {
 756         case BOOT_SOURCE_IFC_NOR:
 757                 env_loc = ENVL_FLASH;
 758                 break;
 759         case BOOT_SOURCE_QSPI_NOR:
 760                 /* FALLTHROUGH */
 761         case BOOT_SOURCE_XSPI_NOR:
 762                 env_loc = ENVL_SPI_FLASH;
 763                 break;
 764         case BOOT_SOURCE_IFC_NAND:
 765                 /* FALLTHROUGH */
 766         case BOOT_SOURCE_QSPI_NAND:
 767                 /* FALLTHROUGH */
 768         case BOOT_SOURCE_XSPI_NAND:
 769                 env_loc = ENVL_NAND;
 770                 break;
 771         case BOOT_SOURCE_SD_MMC:
 772                 /* FALLTHROUGH */
 773         case BOOT_SOURCE_SD_MMC2:
 774                 env_loc =  ENVL_MMC;
 775                 break;
 776         case BOOT_SOURCE_I2C1_EXTENDED:
 777                 /* FALLTHROUGH */
 778         default:
 779                 break;
 780         }
 781
 782 #ifdef CONFIG_CHAIN_OF_TRUST
 783 done:
 784 #endif
 785         return env_loc;
 786 }
 787 #endif  /* CONFIG_TFABOOT */
 788
 789 u32 initiator_type(u32 cluster, int init_id)
 790 {
 791         struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 792         u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
 793         u32 type = 0;
 794
 795         type = gur_in32(&gur->tp_ityp[idx]);
 796         if (type & TP_ITYP_AV)
 797                 return type;
 798
 799         return 0;
 800 }
 801
 802 u32 cpu_pos_mask(void)
 803 {
 804         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 805         int i = 0;
 806         u32 cluster, type, mask = 0;
 807
 808         do {
 809                 int j;
 810
 811                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 812                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 813                         type = initiator_type(cluster, j);
 814                         if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
 815                                 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
 816                 }
 817                 i++;
 818         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 819
 820         return mask;
 821 }
 822
 823 u32 cpu_mask(void)
 824 {
 825         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 826         int i = 0, count = 0;
 827         u32 cluster, type, mask = 0;
 828
 829         do {
 830                 int j;
 831
 832                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 833                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 834                         type = initiator_type(cluster, j);
 835                         if (type) {
 836                                 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
 837                                         mask |= 1 << count;
 838                                 count++;
 839                         }
 840                 }
 841                 i++;
 842         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 843
 844         return mask;
 845 }
 846
 847 /*
 848  * Return the number of cores on this SOC.
 849  */
 850 int cpu_numcores(void)
 851 {
 852         return hweight32(cpu_mask());
 853 }
 854
 855 int fsl_qoriq_core_to_cluster(unsigned int core)
 856 {
 857         struct ccsr_gur __iomem *gur =
 858                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 859         int i = 0, count = 0;
 860         u32 cluster;
 861
 862         do {
 863                 int j;
 864
 865                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 866                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 867                         if (initiator_type(cluster, j)) {
 868                                 if (count == core)
 869                                         return i;
 870                                 count++;
 871                         }
 872                 }
 873                 i++;
 874         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 875
 876         return -1;      /* cannot identify the cluster */
 877 }
 878
 879 u32 fsl_qoriq_core_to_type(unsigned int core)
 880 {
 881         struct ccsr_gur __iomem *gur =
 882                 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 883         int i = 0, count = 0;
 884         u32 cluster, type;
 885
 886         do {
 887                 int j;
 888
 889                 cluster = gur_in32(&gur->tp_cluster[i].lower);
 890                 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 891                         type = initiator_type(cluster, j);
 892                         if (type) {
 893                                 if (count == core)
 894                                         return type;
 895                                 count++;
 896                         }
 897                 }
 898                 i++;
 899         } while ((cluster & TP_CLUSTER_EOC) == 0x0);
 900
 901         return -1;      /* cannot identify the cluster */
 902 }
 903
 904 #ifndef CONFIG_FSL_LSCH3
 905 uint get_svr(void)
 906 {
 907         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 908
 909         return gur_in32(&gur->svr);
 910 }
 911 #endif
 912
 913 #ifdef CONFIG_DISPLAY_CPUINFO
 914 int print_cpuinfo(void)
 915 {
 916         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 917         struct sys_info sysinfo;
 918         char buf[32];
 919         unsigned int i, core;
 920         u32 type, rcw, svr = gur_in32(&gur->svr);
 921
 922         puts("SoC: ");
 923
 924         cpu_name(buf);
 925         printf(" %s (0x%x)\n", buf, svr);
 926         memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 927         get_sys_info(&sysinfo);
 928         puts("Clock Configuration:");
 929         for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
 930                 if (!(i % 3))
 931                         puts("\n       ");
 932                 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
 933                 printf("CPU%d(%s):%-4s MHz  ", core,
 934                        type == TY_ITYP_VER_A7 ? "A7 " :
 935                        (type == TY_ITYP_VER_A53 ? "A53" :
 936                        (type == TY_ITYP_VER_A57 ? "A57" :
 937                        (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
 938                        strmhz(buf, sysinfo.freq_processor[core]));
 939         }
 940         /* Display platform clock as Bus frequency. */
 941         printf("\n       Bus:      %-4s MHz  ",
 942                strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
 943         printf("DDR:      %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
 944 #ifdef CONFIG_SYS_DPAA_FMAN
 945         printf("  FMAN:     %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
 946 #endif
 947 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 948         if (soc_has_dp_ddr()) {
 949                 printf("     DP-DDR:   %-4s MT/s",
 950                        strmhz(buf, sysinfo.freq_ddrbus2));
 951         }
 952 #endif
 953         puts("\n");
 954
 955         /*
 956          * Display the RCW, so that no one gets confused as to what RCW
 957          * we're actually using for this boot.
 958          */
 959         puts("Reset Configuration Word (RCW):");
 960         for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
 961                 rcw = gur_in32(&gur->rcwsr[i]);
 962                 if ((i % 4) == 0)
 963                         printf("\n       %08x:", i * 4);
 964                 printf(" %08x", rcw);
 965         }
 966         puts("\n");
 967
 968         return 0;
 969 }
 970 #endif
 971
 972 #ifdef CONFIG_FSL_ESDHC
 973 int cpu_mmc_init(bd_t *bis)
 974 {
 975         return fsl_esdhc_mmc_init(bis);
 976 }
 977 #endif
 978
 979 int cpu_eth_init(bd_t *bis)
 980 {
 981         int error = 0;
 982
 983 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 984         error = fsl_mc_ldpaa_init(bis);
 985 #endif
 986 #ifdef CONFIG_FMAN_ENET
 987         fm_standard_init(bis);
 988 #endif
 989         return error;
 990 }
 991
 992 static inline int check_psci(void)
 993 {
 994         unsigned int psci_ver;
 995
 996         psci_ver = sec_firmware_support_psci_version();
 997         if (psci_ver == PSCI_INVALID_VER)
 998                 return 1;
 999
1000         return 0;
1001 }
1002
1003 static void config_core_prefetch(void)
1004 {
1005         char *buf = NULL;
1006         char buffer[HWCONFIG_BUFFER_SIZE];
1007         const char *prefetch_arg = NULL;
1008         size_t arglen;
1009         unsigned int mask;
1010         struct pt_regs regs;
1011
1012         if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
1013                 buf = buffer;
1014
1015         prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
1016                                          &arglen, buf);
1017
1018         if (prefetch_arg) {
1019                 mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
1020                 if (mask & 0x1) {
1021                         printf("Core0 prefetch can't be disabled\n");
1022                         return;
1023                 }
1024
1025 #define SIP_PREFETCH_DISABLE_64 0xC200FF13
1026                 regs.regs[0] = SIP_PREFETCH_DISABLE_64;
1027                 regs.regs[1] = mask;
1028                 smc_call(&regs);
1029
1030                 if (regs.regs[0])
1031                         printf("Prefetch disable config failed for mask ");
1032                 else
1033                         printf("Prefetch disable config passed for mask ");
1034                 printf("0x%x\n", mask);
1035         }
1036 }
1037
1038 int arch_early_init_r(void)
1039 {
1040 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
1041         u32 svr_dev_id;
1042         /*
1043          * erratum A009635 is valid only for LS2080A SoC and
1044          * its personalitiesi
1045          */
1046         svr_dev_id = get_svr();
1047         if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1048                 erratum_a009635();
1049 #endif
1050 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
1051         erratum_a009942_check_cpo();
1052 #endif
1053         if (check_psci()) {
1054                 debug("PSCI: PSCI does not exist.\n");
1055
1056                 /* if PSCI does not exist, boot secondary cores here */
1057                 if (fsl_layerscape_wake_seconday_cores())
1058                         printf("Did not wake secondary cores\n");
1059         }
1060
1061 #ifdef CONFIG_SYS_FSL_HAS_RGMII
1062         fsl_rgmii_init();
1063 #endif
1064
1065         config_core_prefetch();
1066
1067 #ifdef CONFIG_SYS_HAS_SERDES
1068         fsl_serdes_init();
1069 #endif
1070 #ifdef CONFIG_FMAN_ENET
1071         fman_enet_init();
1072 #endif
1073 #ifdef CONFIG_SYS_DPAA_QBMAN
1074         setup_qbman_portals();
1075 #endif
1076         return 0;
1077 }
1078
1079 int timer_init(void)
1080 {
1081         u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
1082 #ifdef CONFIG_FSL_LSCH3
1083         u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
1084 #endif
1085 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
1086         u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
1087         u32 svr_dev_id;
1088 #endif
1089 #ifdef COUNTER_FREQUENCY_REAL
1090         unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
1091
1092         /* Update with accurate clock frequency */
1093         if (current_el() == 3)
1094                 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
1095 #endif
1096
1097 #ifdef CONFIG_FSL_LSCH3
1098         /* Enable timebase for all clusters.
1099          * It is safe to do so even some clusters are not enabled.
1100          */
1101         out_le32(cltbenr, 0xf);
1102 #endif
1103
1104 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
1105         /*
1106          * In certain Layerscape SoCs, the clock for each core's
1107          * has an enable bit in the PMU Physical Core Time Base Enable
1108          * Register (PCTBENR), which allows the watchdog to operate.
1109          */
1110         setbits_le32(pctbenr, 0xff);
1111         /*
1112          * For LS2080A SoC and its personalities, timer controller
1113          * offset is different
1114          */
1115         svr_dev_id = get_svr();
1116         if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1117                 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
1118
1119 #endif
1120
1121         /* Enable clock for timer
1122          * This is a global setting.
1123          */
1124         out_le32(cntcr, 0x1);
1125
1126         return 0;
1127 }
1128
1129 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
1130
1131 void __efi_runtime reset_cpu(ulong addr)
1132 {
1133         u32 val;
1134
1135         /* Raise RESET_REQ_B */
1136         val = scfg_in32(rstcr);
1137         val |= 0x02;
1138         scfg_out32(rstcr, val);
1139 }
1140
1141 #ifdef CONFIG_EFI_LOADER
1142
1143 void __efi_runtime EFIAPI efi_reset_system(
1144                        enum efi_reset_type reset_type,
1145                        efi_status_t reset_status,
1146                        unsigned long data_size, void *reset_data)
1147 {
1148         switch (reset_type) {
1149         case EFI_RESET_COLD:
1150         case EFI_RESET_WARM:
1151         case EFI_RESET_PLATFORM_SPECIFIC:
1152                 reset_cpu(0);
1153                 break;
1154         case EFI_RESET_SHUTDOWN:
1155                 /* Nothing we can do */
1156                 break;
1157         }
1158
1159         while (1) { }
1160 }
1161
1162 efi_status_t efi_reset_system_init(void)
1163 {
1164         return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
1165 }
1166
1167 #endif
1168
1169 /*
1170  * Calculate reserved memory with given memory bank
1171  * Return aligned memory size on success
1172  * Return (ram_size + needed size) for failure
1173  */
1174 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
1175 {
1176         phys_size_t ram_top = ram_size;
1177
1178 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1179         ram_top = mc_get_dram_block_size();
1180         if (ram_top > ram_size)
1181                 return ram_size + ram_top;
1182
1183         ram_top = ram_size - ram_top;
1184         /* The start address of MC reserved memory needs to be aligned. */
1185         ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
1186 #endif
1187
1188         return ram_size - ram_top;
1189 }
1190
1191 phys_size_t get_effective_memsize(void)
1192 {
1193         phys_size_t ea_size, rem = 0;
1194
1195         /*
1196          * For ARMv8 SoCs, DDR memory is split into two or three regions. The
1197          * first region is 2GB space at 0x8000_0000. Secure memory needs to
1198          * allocated from first region. If the memory extends to  the second
1199          * region (or the third region if applicable), Management Complex (MC)
1200          * memory should be put into the highest region, i.e. the end of DDR
1201          * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
1202          * U-Boot doesn't relocate itself into higher address. Should DDR be
1203          * configured to skip the first region, this function needs to be
1204          * adjusted.
1205          */
1206         if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
1207                 ea_size = CONFIG_MAX_MEM_MAPPED;
1208                 rem = gd->ram_size - ea_size;
1209         } else {
1210                 ea_size = gd->ram_size;
1211         }
1212
1213 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1214         /* Check if we have enough space for secure memory */
1215         if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
1216                 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1217         else
1218                 printf("Error: No enough space for secure memory.\n");
1219 #endif
1220         /* Check if we have enough memory for MC */
1221         if (rem < board_reserve_ram_top(rem)) {
1222                 /* Not enough memory in high region to reserve */
1223                 if (ea_size > board_reserve_ram_top(ea_size))
1224                         ea_size -= board_reserve_ram_top(ea_size);
1225                 else
1226                         printf("Error: No enough space for reserved memory.\n");
1227         }
1228
1229         return ea_size;
1230 }
1231
1232 int dram_init_banksize(void)
1233 {
1234 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1235         phys_size_t dp_ddr_size;
1236 #endif
1237
1238         /*
1239          * gd->ram_size has the total size of DDR memory, less reserved secure
1240          * memory. The DDR extends from low region to high region(s) presuming
1241          * no hole is created with DDR configuration. gd->arch.secure_ram tracks
1242          * the location of secure memory. gd->arch.resv_ram tracks the location
1243          * of reserved memory for Management Complex (MC). Because gd->ram_size
1244          * is reduced by this function if secure memory is reserved, checking
1245          * gd->arch.secure_ram should be done to avoid running it repeatedly.
1246          */
1247
1248 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1249         if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
1250                 debug("No need to run again, skip %s\n", __func__);
1251
1252                 return 0;
1253         }
1254 #endif
1255
1256         gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
1257         if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
1258                 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
1259                 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
1260                 gd->bd->bi_dram[1].size = gd->ram_size -
1261                                           CONFIG_SYS_DDR_BLOCK1_SIZE;
1262 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1263                 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
1264                         gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
1265                         gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
1266                                                   CONFIG_SYS_DDR_BLOCK2_SIZE;
1267                         gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
1268                 }
1269 #endif
1270         } else {
1271                 gd->bd->bi_dram[0].size = gd->ram_size;
1272         }
1273 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1274         if (gd->bd->bi_dram[0].size >
1275                                 CONFIG_SYS_MEM_RESERVE_SECURE) {
1276                 gd->bd->bi_dram[0].size -=
1277                                 CONFIG_SYS_MEM_RESERVE_SECURE;
1278                 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
1279                                       gd->bd->bi_dram[0].size;
1280                 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
1281                 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1282         }
1283 #endif  /* CONFIG_SYS_MEM_RESERVE_SECURE */
1284
1285 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1286         /* Assign memory for MC */
1287 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1288         if (gd->bd->bi_dram[2].size >=
1289             board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1290                 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1291                             gd->bd->bi_dram[2].size -
1292                             board_reserve_ram_top(gd->bd->bi_dram[2].size);
1293         } else
1294 #endif
1295         {
1296                 if (gd->bd->bi_dram[1].size >=
1297                     board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1298                         gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1299                                 gd->bd->bi_dram[1].size -
1300                                 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1301                 } else if (gd->bd->bi_dram[0].size >
1302                            board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1303                         gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1304                                 gd->bd->bi_dram[0].size -
1305                                 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1306                 }
1307         }
1308 #endif  /* CONFIG_FSL_MC_ENET */
1309
1310 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1311 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1312 #error "This SoC shouldn't have DP DDR"
1313 #endif
1314         if (soc_has_dp_ddr()) {
1315                 /* initialize DP-DDR here */
1316                 puts("DP-DDR:  ");
1317                 /*
1318                  * DDR controller use 0 as the base address for binding.
1319                  * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
1320                  */
1321                 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
1322                                           CONFIG_DP_DDR_CTRL,
1323                                           CONFIG_DP_DDR_NUM_CTRLS,
1324                                           CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
1325                                           NULL, NULL, NULL);
1326                 if (dp_ddr_size) {
1327                         gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
1328                         gd->bd->bi_dram[2].size = dp_ddr_size;
1329                 } else {
1330                         puts("Not detected");
1331                 }
1332         }
1333 #endif
1334
1335 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1336         debug("%s is called. gd->ram_size is reduced to %lu\n",
1337               __func__, (ulong)gd->ram_size);
1338 #endif
1339
1340         return 0;
1341 }
1342
1343 #if CONFIG_IS_ENABLED(EFI_LOADER)
1344 void efi_add_known_memory(void)
1345 {
1346         int i;
1347         phys_addr_t ram_start, start;
1348         phys_size_t ram_size;
1349         u64 pages;
1350
1351         /* Add RAM */
1352         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
1353 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1354 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1355 #error "This SoC shouldn't have DP DDR"
1356 #endif
1357                 if (i == 2)
1358                         continue;       /* skip DP-DDR */
1359 #endif
1360                 ram_start = gd->bd->bi_dram[i].start;
1361                 ram_size = gd->bd->bi_dram[i].size;
1362 #ifdef CONFIG_RESV_RAM
1363                 if (gd->arch.resv_ram >= ram_start &&
1364                     gd->arch.resv_ram < ram_start + ram_size)
1365                         ram_size = gd->arch.resv_ram - ram_start;
1366 #endif
1367                 start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
1368                 pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
1369
1370                 efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY,
1371                                    false);
1372         }
1373 }
1374 #endif
1375
1376 /*
1377  * Before DDR size is known, early MMU table have DDR mapped as device memory
1378  * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
1379  * needs to be set for these mappings.
1380  * If a special case configures DDR with holes in the mapping, the holes need
1381  * to be marked as invalid. This is not implemented in this function.
1382  */
1383 void update_early_mmu_table(void)
1384 {
1385         if (!gd->arch.tlb_addr)
1386                 return;
1387
1388         if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
1389                 mmu_change_region_attr(
1390                                         CONFIG_SYS_SDRAM_BASE,
1391                                         gd->ram_size,
1392                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1393                                         PTE_BLOCK_OUTER_SHARE           |
1394                                         PTE_BLOCK_NS                    |
1395                                         PTE_TYPE_VALID);
1396         } else {
1397                 mmu_change_region_attr(
1398                                         CONFIG_SYS_SDRAM_BASE,
1399                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
1400                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1401                                         PTE_BLOCK_OUTER_SHARE           |
1402                                         PTE_BLOCK_NS                    |
1403                                         PTE_TYPE_VALID);
1404 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1405 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
1406 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
1407 #endif
1408                 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
1409                     CONFIG_SYS_DDR_BLOCK2_SIZE) {
1410                         mmu_change_region_attr(
1411                                         CONFIG_SYS_DDR_BLOCK2_BASE,
1412                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
1413                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1414                                         PTE_BLOCK_OUTER_SHARE           |
1415                                         PTE_BLOCK_NS                    |
1416                                         PTE_TYPE_VALID);
1417                         mmu_change_region_attr(
1418                                         CONFIG_SYS_DDR_BLOCK3_BASE,
1419                                         gd->ram_size -
1420                                         CONFIG_SYS_DDR_BLOCK1_SIZE -
1421                                         CONFIG_SYS_DDR_BLOCK2_SIZE,
1422                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1423                                         PTE_BLOCK_OUTER_SHARE           |
1424                                         PTE_BLOCK_NS                    |
1425                                         PTE_TYPE_VALID);
1426                 } else
1427 #endif
1428                 {
1429                         mmu_change_region_attr(
1430                                         CONFIG_SYS_DDR_BLOCK2_BASE,
1431                                         gd->ram_size -
1432                                         CONFIG_SYS_DDR_BLOCK1_SIZE,
1433                                         PTE_BLOCK_MEMTYPE(MT_NORMAL)    |
1434                                         PTE_BLOCK_OUTER_SHARE           |
1435                                         PTE_BLOCK_NS                    |
1436                                         PTE_TYPE_VALID);
1437                 }
1438         }
1439 }
1440
1441 __weak int dram_init(void)
1442 {
1443         fsl_initdram();
1444 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
1445         defined(CONFIG_SPL_BUILD)
1446         /* This will break-before-make MMU for DDR */
1447         update_early_mmu_table();
1448 #endif
1449
1450         return 0;
1451 }