3 * Copyright 2014-2015 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <fsl_ddr_sdram.h>
11 #include <linux/errno.h>
12 #include <asm/system.h>
13 #include <asm/armv8/mmu.h>
15 #include <asm/arch/fsl_serdes.h>
16 #include <asm/arch/soc.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/speed.h>
19 #include <fsl_immap.h>
20 #include <asm/arch/mp.h>
21 #include <efi_loader.h>
23 #include <fsl-mc/fsl_mc.h>
24 #ifdef CONFIG_FSL_ESDHC
25 #include <fsl_esdhc.h>
27 #include <asm/armv8/sec_firmware.h>
28 #ifdef CONFIG_SYS_FSL_DDR
31 #include <asm/arch/clock.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 struct mm_region *mem_map = early_map;
37 void cpu_name(char *name)
39 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
40 unsigned int i, svr, ver;
42 svr = gur_in32(&gur->svr);
43 ver = SVR_SOC_VER(svr);
45 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
46 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
47 strcpy(name, cpu_type_list[i].name);
49 if (IS_E_PROCESSOR(svr))
52 sprintf(name + strlen(name), " Rev%d.%d",
53 SVR_MAJ(svr), SVR_MIN(svr));
57 if (i == ARRAY_SIZE(cpu_type_list))
58 strcpy(name, "unknown");
61 #ifndef CONFIG_SYS_DCACHE_OFF
63 * To start MMU before DDR is available, we create MMU table in SRAM.
64 * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
65 * levels of translation tables here to cover 40-bit address space.
66 * We use 4KB granule size, with 40 bits physical address, T0SZ=24
67 * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
68 * Note, the debug print in cache_v8.c is not usable for debugging
69 * these early MMU tables because UART is not yet available.
71 static inline void early_mmu_setup(void)
73 unsigned int el = current_el();
75 /* global data is already setup, no allocation yet */
76 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
77 gd->arch.tlb_fillptr = gd->arch.tlb_addr;
78 gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
80 /* Create early page tables */
83 /* point TTBR to the new table */
84 set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
85 get_tcr(el, NULL, NULL) &
86 ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
89 set_sctlr(get_sctlr() | CR_M);
92 static void fix_pcie_mmu_map(void)
94 #ifdef CONFIG_ARCH_LS2080A
97 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
99 svr = gur_in32(&gur->svr);
100 ver = SVR_SOC_VER(svr);
102 /* Fix PCIE base and size for LS2088A */
103 if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
104 (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
105 (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
106 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
107 switch (final_map[i].phys) {
108 case CONFIG_SYS_PCIE1_PHYS_ADDR:
109 final_map[i].phys = 0x2000000000ULL;
110 final_map[i].virt = 0x2000000000ULL;
111 final_map[i].size = 0x800000000ULL;
113 case CONFIG_SYS_PCIE2_PHYS_ADDR:
114 final_map[i].phys = 0x2800000000ULL;
115 final_map[i].virt = 0x2800000000ULL;
116 final_map[i].size = 0x800000000ULL;
118 case CONFIG_SYS_PCIE3_PHYS_ADDR:
119 final_map[i].phys = 0x3000000000ULL;
120 final_map[i].virt = 0x3000000000ULL;
121 final_map[i].size = 0x800000000ULL;
123 case CONFIG_SYS_PCIE4_PHYS_ADDR:
124 final_map[i].phys = 0x3800000000ULL;
125 final_map[i].virt = 0x3800000000ULL;
126 final_map[i].size = 0x800000000ULL;
137 * The final tables look similar to early tables, but different in detail.
138 * These tables are in DRAM. Sub tables are added to enable cache for
141 * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
142 * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
144 static inline void final_mmu_setup(void)
146 u64 tlb_addr_save = gd->arch.tlb_addr;
147 unsigned int el = current_el();
150 /* fix the final_map before filling in the block entries */
155 /* Update mapping for DDR to actual size */
156 for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
158 * Find the entry for DDR mapping and update the address and
159 * size. Zero-sized mapping will be skipped when creating MMU
162 switch (final_map[index].virt) {
163 case CONFIG_SYS_FSL_DRAM_BASE1:
164 final_map[index].virt = gd->bd->bi_dram[0].start;
165 final_map[index].phys = gd->bd->bi_dram[0].start;
166 final_map[index].size = gd->bd->bi_dram[0].size;
168 #ifdef CONFIG_SYS_FSL_DRAM_BASE2
169 case CONFIG_SYS_FSL_DRAM_BASE2:
170 #if (CONFIG_NR_DRAM_BANKS >= 2)
171 final_map[index].virt = gd->bd->bi_dram[1].start;
172 final_map[index].phys = gd->bd->bi_dram[1].start;
173 final_map[index].size = gd->bd->bi_dram[1].size;
175 final_map[index].size = 0;
179 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
180 case CONFIG_SYS_FSL_DRAM_BASE3:
181 #if (CONFIG_NR_DRAM_BANKS >= 3)
182 final_map[index].virt = gd->bd->bi_dram[2].start;
183 final_map[index].phys = gd->bd->bi_dram[2].start;
184 final_map[index].size = gd->bd->bi_dram[2].size;
186 final_map[index].size = 0;
195 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
196 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
199 * Only use gd->arch.secure_ram if the address is
200 * recalculated. Align to 4KB for MMU table.
202 /* put page tables in secure ram */
203 index = ARRAY_SIZE(final_map) - 2;
204 gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
205 final_map[index].virt = gd->arch.secure_ram & ~0x3;
206 final_map[index].phys = final_map[index].virt;
207 final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
208 final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
209 gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
210 tlb_addr_save = gd->arch.tlb_addr;
212 /* Use allocated (board_f.c) memory for TLB */
213 tlb_addr_save = gd->arch.tlb_allocated;
214 gd->arch.tlb_addr = tlb_addr_save;
219 /* Reset the fill ptr */
220 gd->arch.tlb_fillptr = tlb_addr_save;
222 /* Create normal system page tables */
225 /* Create emergency page tables */
226 gd->arch.tlb_addr = gd->arch.tlb_fillptr;
227 gd->arch.tlb_emerg = gd->arch.tlb_addr;
229 gd->arch.tlb_addr = tlb_addr_save;
231 /* Disable cache and MMU */
232 dcache_disable(); /* TLBs are invalidated */
233 invalidate_icache_all();
235 /* point TTBR to the new table */
236 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
239 set_sctlr(get_sctlr() | CR_M);
242 u64 get_page_table_size(void)
247 int arch_cpu_init(void)
250 * This function is called before U-Boot relocates itself to speed up
251 * on system running. It is not necessary to run if performance is not
252 * critical. Skip if MMU is already enabled by SPL or other means.
254 if (get_sctlr() & CR_M)
258 __asm_invalidate_dcache_all();
259 __asm_invalidate_tlb_all();
261 set_sctlr(get_sctlr() | CR_C);
271 * This function is called from common/board_r.c.
272 * It recreates MMU table in main memory.
274 void enable_caches(void)
277 __asm_invalidate_tlb_all();
283 u32 initiator_type(u32 cluster, int init_id)
285 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
286 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
289 type = gur_in32(&gur->tp_ityp[idx]);
290 if (type & TP_ITYP_AV)
296 u32 cpu_pos_mask(void)
298 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
300 u32 cluster, type, mask = 0;
305 cluster = gur_in32(&gur->tp_cluster[i].lower);
306 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
307 type = initiator_type(cluster, j);
308 if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
309 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
312 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
319 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
320 int i = 0, count = 0;
321 u32 cluster, type, mask = 0;
326 cluster = gur_in32(&gur->tp_cluster[i].lower);
327 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
328 type = initiator_type(cluster, j);
330 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
336 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
342 * Return the number of cores on this SOC.
344 int cpu_numcores(void)
346 return hweight32(cpu_mask());
349 int fsl_qoriq_core_to_cluster(unsigned int core)
351 struct ccsr_gur __iomem *gur =
352 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
353 int i = 0, count = 0;
359 cluster = gur_in32(&gur->tp_cluster[i].lower);
360 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
361 if (initiator_type(cluster, j)) {
368 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
370 return -1; /* cannot identify the cluster */
373 u32 fsl_qoriq_core_to_type(unsigned int core)
375 struct ccsr_gur __iomem *gur =
376 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
377 int i = 0, count = 0;
383 cluster = gur_in32(&gur->tp_cluster[i].lower);
384 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
385 type = initiator_type(cluster, j);
393 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
395 return -1; /* cannot identify the cluster */
398 #ifndef CONFIG_FSL_LSCH3
401 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
403 return gur_in32(&gur->svr);
407 #ifdef CONFIG_DISPLAY_CPUINFO
408 int print_cpuinfo(void)
410 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
411 struct sys_info sysinfo;
413 unsigned int i, core;
414 u32 type, rcw, svr = gur_in32(&gur->svr);
419 printf(" %s (0x%x)\n", buf, svr);
420 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
421 get_sys_info(&sysinfo);
422 puts("Clock Configuration:");
423 for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
426 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
427 printf("CPU%d(%s):%-4s MHz ", core,
428 type == TY_ITYP_VER_A7 ? "A7 " :
429 (type == TY_ITYP_VER_A53 ? "A53" :
430 (type == TY_ITYP_VER_A57 ? "A57" :
431 (type == TY_ITYP_VER_A72 ? "A72" : " "))),
432 strmhz(buf, sysinfo.freq_processor[core]));
434 /* Display platform clock as Bus frequency. */
435 printf("\n Bus: %-4s MHz ",
436 strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
437 printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
438 #ifdef CONFIG_SYS_DPAA_FMAN
439 printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
441 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
442 if (soc_has_dp_ddr()) {
443 printf(" DP-DDR: %-4s MT/s",
444 strmhz(buf, sysinfo.freq_ddrbus2));
450 * Display the RCW, so that no one gets confused as to what RCW
451 * we're actually using for this boot.
453 puts("Reset Configuration Word (RCW):");
454 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
455 rcw = gur_in32(&gur->rcwsr[i]);
457 printf("\n %08x:", i * 4);
458 printf(" %08x", rcw);
466 #ifdef CONFIG_FSL_ESDHC
467 int cpu_mmc_init(bd_t *bis)
469 return fsl_esdhc_mmc_init(bis);
473 int cpu_eth_init(bd_t *bis)
477 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
478 error = fsl_mc_ldpaa_init(bis);
480 #ifdef CONFIG_FMAN_ENET
481 fm_standard_init(bis);
486 static inline int check_psci(void)
488 unsigned int psci_ver;
490 psci_ver = sec_firmware_support_psci_version();
491 if (psci_ver == PSCI_INVALID_VER)
497 int arch_early_init_r(void)
499 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
502 * erratum A009635 is valid only for LS2080A SoC and
505 svr_dev_id = get_svr() >> 16;
506 if (svr_dev_id == SVR_DEV_LS2080A)
509 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
510 erratum_a009942_check_cpo();
513 debug("PSCI: PSCI does not exist.\n");
515 /* if PSCI does not exist, boot secondary cores here */
516 if (fsl_layerscape_wake_seconday_cores())
517 printf("Did not wake secondary cores\n");
520 #ifdef CONFIG_SYS_FSL_HAS_RGMII
524 #ifdef CONFIG_SYS_HAS_SERDES
527 #ifdef CONFIG_FMAN_ENET
535 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
536 #ifdef CONFIG_FSL_LSCH3
537 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
539 #ifdef CONFIG_ARCH_LS2080A
540 u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
543 #ifdef COUNTER_FREQUENCY_REAL
544 unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
546 /* Update with accurate clock frequency */
547 if (current_el() == 3)
548 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
551 #ifdef CONFIG_FSL_LSCH3
552 /* Enable timebase for all clusters.
553 * It is safe to do so even some clusters are not enabled.
555 out_le32(cltbenr, 0xf);
558 #ifdef CONFIG_ARCH_LS2080A
560 * In certain Layerscape SoCs, the clock for each core's
561 * has an enable bit in the PMU Physical Core Time Base Enable
562 * Register (PCTBENR), which allows the watchdog to operate.
564 setbits_le32(pctbenr, 0xff);
566 * For LS2080A SoC and its personalities, timer controller
567 * offset is different
569 svr_dev_id = get_svr() >> 16;
570 if (svr_dev_id == SVR_DEV_LS2080A)
571 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
575 /* Enable clock for timer
576 * This is a global setting.
578 out_le32(cntcr, 0x1);
583 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
585 void __efi_runtime reset_cpu(ulong addr)
589 /* Raise RESET_REQ_B */
590 val = scfg_in32(rstcr);
592 scfg_out32(rstcr, val);
595 #ifdef CONFIG_EFI_LOADER
597 void __efi_runtime EFIAPI efi_reset_system(
598 enum efi_reset_type reset_type,
599 efi_status_t reset_status,
600 unsigned long data_size, void *reset_data)
602 switch (reset_type) {
607 case EFI_RESET_SHUTDOWN:
608 /* Nothing we can do */
615 void efi_reset_system_init(void)
617 efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
622 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
624 phys_size_t ram_top = ram_size;
626 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
627 /* The start address of MC reserved memory needs to be aligned. */
628 ram_top -= mc_get_dram_block_size();
629 ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
632 return ram_size - ram_top;
635 phys_size_t get_effective_memsize(void)
637 phys_size_t ea_size, rem = 0;
640 * For ARMv8 SoCs, DDR memory is split into two or three regions. The
641 * first region is 2GB space at 0x8000_0000. If the memory extends to
642 * the second region (or the third region if applicable), the secure
643 * memory and Management Complex (MC) memory should be put into the
644 * highest region, i.e. the end of DDR memory. CONFIG_MAX_MEM_MAPPED
645 * is set to the size of first region so U-Boot doesn't relocate itself
646 * into higher address. Should DDR be configured to skip the first
647 * region, this function needs to be adjusted.
649 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
650 ea_size = CONFIG_MAX_MEM_MAPPED;
651 rem = gd->ram_size - ea_size;
653 ea_size = gd->ram_size;
656 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
657 /* Check if we have enough space for secure memory */
658 if (rem > CONFIG_SYS_MEM_RESERVE_SECURE) {
659 rem -= CONFIG_SYS_MEM_RESERVE_SECURE;
661 if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE) {
662 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
663 rem = 0; /* Presume MC requires more memory */
665 printf("Error: No enough space for secure memory.\n");
669 /* Check if we have enough memory for MC */
670 if (rem < board_reserve_ram_top(rem)) {
671 /* Not enough memory in high region to reserve */
672 if (ea_size > board_reserve_ram_top(rem))
673 ea_size -= board_reserve_ram_top(rem);
675 printf("Error: No enough space for reserved memory.\n");
681 int dram_init_banksize(void)
683 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
684 phys_size_t dp_ddr_size;
688 * gd->ram_size has the total size of DDR memory, less reserved secure
689 * memory. The DDR extends from low region to high region(s) presuming
690 * no hole is created with DDR configuration. gd->arch.secure_ram tracks
691 * the location of secure memory. gd->arch.resv_ram tracks the location
692 * of reserved memory for Management Complex (MC).
694 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
695 if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
696 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
697 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
698 gd->bd->bi_dram[1].size = gd->ram_size -
699 CONFIG_SYS_DDR_BLOCK1_SIZE;
700 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
701 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
702 gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
703 gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
704 CONFIG_SYS_DDR_BLOCK2_SIZE;
705 gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
709 gd->bd->bi_dram[0].size = gd->ram_size;
711 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
712 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
713 if (gd->bd->bi_dram[2].size >= CONFIG_SYS_MEM_RESERVE_SECURE) {
714 gd->bd->bi_dram[2].size -= CONFIG_SYS_MEM_RESERVE_SECURE;
715 gd->arch.secure_ram = gd->bd->bi_dram[2].start +
716 gd->bd->bi_dram[2].size;
717 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
718 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
722 if (gd->bd->bi_dram[1].size >= CONFIG_SYS_MEM_RESERVE_SECURE) {
723 gd->bd->bi_dram[1].size -=
724 CONFIG_SYS_MEM_RESERVE_SECURE;
725 gd->arch.secure_ram = gd->bd->bi_dram[1].start +
726 gd->bd->bi_dram[1].size;
727 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
728 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
729 } else if (gd->bd->bi_dram[0].size >
730 CONFIG_SYS_MEM_RESERVE_SECURE) {
731 gd->bd->bi_dram[0].size -=
732 CONFIG_SYS_MEM_RESERVE_SECURE;
733 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
734 gd->bd->bi_dram[0].size;
735 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
736 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
739 #endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
741 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
742 /* Assign memory for MC */
743 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
744 if (gd->bd->bi_dram[2].size >=
745 board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
746 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
747 gd->bd->bi_dram[2].size -
748 board_reserve_ram_top(gd->bd->bi_dram[2].size);
752 if (gd->bd->bi_dram[1].size >=
753 board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
754 gd->arch.resv_ram = gd->bd->bi_dram[1].start +
755 gd->bd->bi_dram[1].size -
756 board_reserve_ram_top(gd->bd->bi_dram[1].size);
757 } else if (gd->bd->bi_dram[0].size >
758 board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
759 gd->arch.resv_ram = gd->bd->bi_dram[0].start +
760 gd->bd->bi_dram[0].size -
761 board_reserve_ram_top(gd->bd->bi_dram[0].size);
764 #endif /* CONFIG_FSL_MC_ENET */
766 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
767 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
768 #error "This SoC shouldn't have DP DDR"
770 if (soc_has_dp_ddr()) {
771 /* initialize DP-DDR here */
774 * DDR controller use 0 as the base address for binding.
775 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
777 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
779 CONFIG_DP_DDR_NUM_CTRLS,
780 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
783 gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
784 gd->bd->bi_dram[2].size = dp_ddr_size;
786 puts("Not detected");
794 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
795 void efi_add_known_memory(void)
798 phys_addr_t ram_start, start;
799 phys_size_t ram_size;
803 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
804 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
805 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
806 #error "This SoC shouldn't have DP DDR"
809 continue; /* skip DP-DDR */
811 ram_start = gd->bd->bi_dram[i].start;
812 ram_size = gd->bd->bi_dram[i].size;
813 #ifdef CONFIG_RESV_RAM
814 if (gd->arch.resv_ram >= ram_start &&
815 gd->arch.resv_ram < ram_start + ram_size)
816 ram_size = gd->arch.resv_ram - ram_start;
818 start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
819 pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
821 efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY,
828 * Before DDR size is known, early MMU table have DDR mapped as device memory
829 * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
830 * needs to be set for these mappings.
831 * If a special case configures DDR with holes in the mapping, the holes need
832 * to be marked as invalid. This is not implemented in this function.
834 void update_early_mmu_table(void)
836 if (!gd->arch.tlb_addr)
839 if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
840 mmu_change_region_attr(
841 CONFIG_SYS_SDRAM_BASE,
843 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
844 PTE_BLOCK_OUTER_SHARE |
848 mmu_change_region_attr(
849 CONFIG_SYS_SDRAM_BASE,
850 CONFIG_SYS_DDR_BLOCK1_SIZE,
851 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
852 PTE_BLOCK_OUTER_SHARE |
855 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
856 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
857 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
859 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
860 CONFIG_SYS_DDR_BLOCK2_SIZE) {
861 mmu_change_region_attr(
862 CONFIG_SYS_DDR_BLOCK2_BASE,
863 CONFIG_SYS_DDR_BLOCK2_SIZE,
864 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
865 PTE_BLOCK_OUTER_SHARE |
868 mmu_change_region_attr(
869 CONFIG_SYS_DDR_BLOCK3_BASE,
871 CONFIG_SYS_DDR_BLOCK1_SIZE -
872 CONFIG_SYS_DDR_BLOCK2_SIZE,
873 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
874 PTE_BLOCK_OUTER_SHARE |
880 mmu_change_region_attr(
881 CONFIG_SYS_DDR_BLOCK2_BASE,
883 CONFIG_SYS_DDR_BLOCK1_SIZE,
884 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
885 PTE_BLOCK_OUTER_SHARE |
892 __weak int dram_init(void)
895 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
896 /* This will break-before-make MMU for DDR */
897 update_early_mmu_table();