1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
8 #include <fsl_ddr_sdram.h>
10 #include <linux/errno.h>
11 #include <asm/system.h>
13 #include <asm/armv8/mmu.h>
15 #include <asm/arch/fsl_serdes.h>
16 #include <asm/arch/soc.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/speed.h>
19 #include <fsl_immap.h>
20 #include <asm/arch/mp.h>
21 #include <efi_loader.h>
22 #include <fsl-mc/fsl_mc.h>
23 #ifdef CONFIG_FSL_ESDHC
24 #include <fsl_esdhc.h>
26 #include <asm/armv8/sec_firmware.h>
27 #ifdef CONFIG_SYS_FSL_DDR
30 #include <asm/arch/clock.h>
32 #include <fsl_qbman.h>
35 #include <environment.h>
36 #ifdef CONFIG_CHAIN_OF_TRUST
37 #include <fsl_validate.h>
41 DECLARE_GLOBAL_DATA_PTR;
43 static struct cpu_type cpu_type_list[] = {
44 CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
45 CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
46 CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
47 CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
48 CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
49 CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
50 CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
51 CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
52 CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
53 CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
54 CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
55 CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
56 CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
57 CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
58 CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
59 CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
60 CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
61 CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
62 CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
65 #define EARLY_PGTABLE_SIZE 0x5000
66 static struct mm_region early_map[] = {
67 #ifdef CONFIG_FSL_LSCH3
68 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
69 CONFIG_SYS_FSL_CCSR_SIZE,
70 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
71 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
73 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
74 SYS_FSL_OCRAM_SPACE_SIZE,
75 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
77 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
78 CONFIG_SYS_FSL_QSPI_SIZE1,
79 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
81 /* For IFC Region #1, only the first 4MB is cache-enabled */
82 { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
83 CONFIG_SYS_FSL_IFC_SIZE1_1,
84 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
86 { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
87 CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
88 CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
89 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
91 { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
92 CONFIG_SYS_FSL_IFC_SIZE1,
93 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
96 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
97 CONFIG_SYS_FSL_DRAM_SIZE1,
98 #if defined(CONFIG_TFABOOT) || \
99 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
100 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
101 #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
102 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
104 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
106 #ifdef CONFIG_FSL_IFC
107 /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
108 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
109 CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
110 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
113 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
114 CONFIG_SYS_FSL_DCSR_SIZE,
115 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
116 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
118 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
119 CONFIG_SYS_FSL_DRAM_SIZE2,
120 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
121 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
123 #elif defined(CONFIG_FSL_LSCH2)
124 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
125 CONFIG_SYS_FSL_CCSR_SIZE,
126 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
127 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
129 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
130 SYS_FSL_OCRAM_SPACE_SIZE,
131 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
133 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
134 CONFIG_SYS_FSL_DCSR_SIZE,
135 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
136 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
138 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
139 CONFIG_SYS_FSL_QSPI_SIZE,
140 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
142 #ifdef CONFIG_FSL_IFC
143 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
144 CONFIG_SYS_FSL_IFC_SIZE,
145 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
148 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
149 CONFIG_SYS_FSL_DRAM_SIZE1,
150 #if defined(CONFIG_TFABOOT) || \
151 (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
152 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
153 #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
154 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
156 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
158 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
159 CONFIG_SYS_FSL_DRAM_SIZE2,
160 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
161 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
164 {}, /* list terminator */
167 static struct mm_region final_map[] = {
168 #ifdef CONFIG_FSL_LSCH3
169 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
170 CONFIG_SYS_FSL_CCSR_SIZE,
171 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
172 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
174 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
175 SYS_FSL_OCRAM_SPACE_SIZE,
176 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
178 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
179 CONFIG_SYS_FSL_DRAM_SIZE1,
180 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
181 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
183 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
184 CONFIG_SYS_FSL_QSPI_SIZE1,
185 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
186 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
188 { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
189 CONFIG_SYS_FSL_QSPI_SIZE2,
190 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
191 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
193 #ifdef CONFIG_FSL_IFC
194 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
195 CONFIG_SYS_FSL_IFC_SIZE2,
196 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
197 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
200 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
201 CONFIG_SYS_FSL_DCSR_SIZE,
202 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
203 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
205 { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
206 CONFIG_SYS_FSL_MC_SIZE,
207 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
208 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
210 { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
211 CONFIG_SYS_FSL_NI_SIZE,
212 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
213 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
215 /* For QBMAN portal, only the first 64MB is cache-enabled */
216 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
217 CONFIG_SYS_FSL_QBMAN_SIZE_1,
218 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
219 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
221 { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
222 CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
223 CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
224 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
225 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
227 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
228 CONFIG_SYS_PCIE1_PHYS_SIZE,
229 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
230 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
232 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
233 CONFIG_SYS_PCIE2_PHYS_SIZE,
234 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
235 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
237 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
238 CONFIG_SYS_PCIE3_PHYS_SIZE,
239 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
240 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
242 #ifdef CONFIG_ARCH_LS2080A
243 { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
244 CONFIG_SYS_PCIE4_PHYS_SIZE,
245 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
246 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
249 { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
250 CONFIG_SYS_FSL_WRIOP1_SIZE,
251 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
252 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
254 { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
255 CONFIG_SYS_FSL_AIOP1_SIZE,
256 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
257 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
259 { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
260 CONFIG_SYS_FSL_PEBUF_SIZE,
261 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
262 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
264 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
265 CONFIG_SYS_FSL_DRAM_SIZE2,
266 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
267 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
269 #elif defined(CONFIG_FSL_LSCH2)
270 { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
271 CONFIG_SYS_FSL_BOOTROM_SIZE,
272 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
273 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
275 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
276 CONFIG_SYS_FSL_CCSR_SIZE,
277 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
278 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
280 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
281 SYS_FSL_OCRAM_SPACE_SIZE,
282 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
284 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
285 CONFIG_SYS_FSL_DCSR_SIZE,
286 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
287 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
289 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
290 CONFIG_SYS_FSL_QSPI_SIZE,
291 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
292 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
294 #ifdef CONFIG_FSL_IFC
295 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
296 CONFIG_SYS_FSL_IFC_SIZE,
297 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
300 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
301 CONFIG_SYS_FSL_DRAM_SIZE1,
302 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
303 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
305 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
306 CONFIG_SYS_FSL_QBMAN_SIZE,
307 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
308 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
310 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
311 CONFIG_SYS_FSL_DRAM_SIZE2,
312 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
313 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
315 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
316 CONFIG_SYS_PCIE1_PHYS_SIZE,
317 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
318 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
320 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
321 CONFIG_SYS_PCIE2_PHYS_SIZE,
322 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
323 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
325 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
326 CONFIG_SYS_PCIE3_PHYS_SIZE,
327 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
328 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
330 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
331 CONFIG_SYS_FSL_DRAM_SIZE3,
332 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
333 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
336 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
337 {}, /* space holder for secure mem */
342 struct mm_region *mem_map = early_map;
344 void cpu_name(char *name)
346 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
347 unsigned int i, svr, ver;
349 svr = gur_in32(&gur->svr);
350 ver = SVR_SOC_VER(svr);
352 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
353 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
354 strcpy(name, cpu_type_list[i].name);
356 if (IS_E_PROCESSOR(svr))
359 sprintf(name + strlen(name), " Rev%d.%d",
360 SVR_MAJ(svr), SVR_MIN(svr));
364 if (i == ARRAY_SIZE(cpu_type_list))
365 strcpy(name, "unknown");
368 #ifndef CONFIG_SYS_DCACHE_OFF
370 * To start MMU before DDR is available, we create MMU table in SRAM.
371 * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
372 * levels of translation tables here to cover 40-bit address space.
373 * We use 4KB granule size, with 40 bits physical address, T0SZ=24
374 * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
375 * Note, the debug print in cache_v8.c is not usable for debugging
376 * these early MMU tables because UART is not yet available.
378 static inline void early_mmu_setup(void)
380 unsigned int el = current_el();
382 /* global data is already setup, no allocation yet */
384 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
386 gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
387 gd->arch.tlb_fillptr = gd->arch.tlb_addr;
388 gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
390 /* Create early page tables */
393 /* point TTBR to the new table */
394 set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
395 get_tcr(el, NULL, NULL) &
396 ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
399 set_sctlr(get_sctlr() | CR_M);
402 static void fix_pcie_mmu_map(void)
404 #ifdef CONFIG_ARCH_LS2080A
407 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
409 svr = gur_in32(&gur->svr);
410 ver = SVR_SOC_VER(svr);
412 /* Fix PCIE base and size for LS2088A */
413 if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
414 (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
415 (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
416 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
417 switch (final_map[i].phys) {
418 case CONFIG_SYS_PCIE1_PHYS_ADDR:
419 final_map[i].phys = 0x2000000000ULL;
420 final_map[i].virt = 0x2000000000ULL;
421 final_map[i].size = 0x800000000ULL;
423 case CONFIG_SYS_PCIE2_PHYS_ADDR:
424 final_map[i].phys = 0x2800000000ULL;
425 final_map[i].virt = 0x2800000000ULL;
426 final_map[i].size = 0x800000000ULL;
428 case CONFIG_SYS_PCIE3_PHYS_ADDR:
429 final_map[i].phys = 0x3000000000ULL;
430 final_map[i].virt = 0x3000000000ULL;
431 final_map[i].size = 0x800000000ULL;
433 case CONFIG_SYS_PCIE4_PHYS_ADDR:
434 final_map[i].phys = 0x3800000000ULL;
435 final_map[i].virt = 0x3800000000ULL;
436 final_map[i].size = 0x800000000ULL;
447 * The final tables look similar to early tables, but different in detail.
448 * These tables are in DRAM. Sub tables are added to enable cache for
451 * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
452 * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
454 static inline void final_mmu_setup(void)
456 u64 tlb_addr_save = gd->arch.tlb_addr;
457 unsigned int el = current_el();
460 /* fix the final_map before filling in the block entries */
465 /* Update mapping for DDR to actual size */
466 for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
468 * Find the entry for DDR mapping and update the address and
469 * size. Zero-sized mapping will be skipped when creating MMU
472 switch (final_map[index].virt) {
473 case CONFIG_SYS_FSL_DRAM_BASE1:
474 final_map[index].virt = gd->bd->bi_dram[0].start;
475 final_map[index].phys = gd->bd->bi_dram[0].start;
476 final_map[index].size = gd->bd->bi_dram[0].size;
478 #ifdef CONFIG_SYS_FSL_DRAM_BASE2
479 case CONFIG_SYS_FSL_DRAM_BASE2:
480 #if (CONFIG_NR_DRAM_BANKS >= 2)
481 final_map[index].virt = gd->bd->bi_dram[1].start;
482 final_map[index].phys = gd->bd->bi_dram[1].start;
483 final_map[index].size = gd->bd->bi_dram[1].size;
485 final_map[index].size = 0;
489 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
490 case CONFIG_SYS_FSL_DRAM_BASE3:
491 #if (CONFIG_NR_DRAM_BANKS >= 3)
492 final_map[index].virt = gd->bd->bi_dram[2].start;
493 final_map[index].phys = gd->bd->bi_dram[2].start;
494 final_map[index].size = gd->bd->bi_dram[2].size;
496 final_map[index].size = 0;
505 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
506 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
509 * Only use gd->arch.secure_ram if the address is
510 * recalculated. Align to 4KB for MMU table.
512 /* put page tables in secure ram */
513 index = ARRAY_SIZE(final_map) - 2;
514 gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
515 final_map[index].virt = gd->arch.secure_ram & ~0x3;
516 final_map[index].phys = final_map[index].virt;
517 final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
518 final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
519 gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
520 tlb_addr_save = gd->arch.tlb_addr;
522 /* Use allocated (board_f.c) memory for TLB */
523 tlb_addr_save = gd->arch.tlb_allocated;
524 gd->arch.tlb_addr = tlb_addr_save;
529 /* Reset the fill ptr */
530 gd->arch.tlb_fillptr = tlb_addr_save;
532 /* Create normal system page tables */
535 /* Create emergency page tables */
536 gd->arch.tlb_addr = gd->arch.tlb_fillptr;
537 gd->arch.tlb_emerg = gd->arch.tlb_addr;
539 gd->arch.tlb_addr = tlb_addr_save;
541 /* Disable cache and MMU */
542 dcache_disable(); /* TLBs are invalidated */
543 invalidate_icache_all();
545 /* point TTBR to the new table */
546 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
549 set_sctlr(get_sctlr() | CR_M);
552 u64 get_page_table_size(void)
557 int arch_cpu_init(void)
560 * This function is called before U-Boot relocates itself to speed up
561 * on system running. It is not necessary to run if performance is not
562 * critical. Skip if MMU is already enabled by SPL or other means.
564 if (get_sctlr() & CR_M)
568 __asm_invalidate_dcache_all();
569 __asm_invalidate_tlb_all();
571 set_sctlr(get_sctlr() | CR_C);
581 * This function is called from common/board_r.c.
582 * It recreates MMU table in main memory.
584 void enable_caches(void)
587 __asm_invalidate_tlb_all();
591 #endif /* CONFIG_SYS_DCACHE_OFF */
593 #ifdef CONFIG_TFABOOT
594 enum boot_src __get_boot_src(u32 porsr1)
596 enum boot_src src = BOOT_SOURCE_RESERVED;
597 u32 rcw_src = (porsr1 & RCW_SRC_MASK) >> RCW_SRC_BIT;
598 #if !defined(CONFIG_FSL_LSCH3_2)
601 debug("%s: rcw_src 0x%x\n", __func__, rcw_src);
603 #if defined(CONFIG_FSL_LSCH3)
604 #if defined(CONFIG_FSL_LSCH3_2)
606 case RCW_SRC_SDHC1_VAL:
607 src = BOOT_SOURCE_SD_MMC;
609 case RCW_SRC_SDHC2_VAL:
610 src = BOOT_SOURCE_SD_MMC2;
612 case RCW_SRC_I2C1_VAL:
613 src = BOOT_SOURCE_I2C1_EXTENDED;
615 case RCW_SRC_FLEXSPI_NAND2K_VAL:
616 src = BOOT_SOURCE_XSPI_NAND;
618 case RCW_SRC_FLEXSPI_NAND4K_VAL:
619 src = BOOT_SOURCE_XSPI_NAND;
621 case RCW_SRC_RESERVED_1_VAL:
622 src = BOOT_SOURCE_RESERVED;
624 case RCW_SRC_FLEXSPI_NOR_24B:
625 src = BOOT_SOURCE_XSPI_NOR;
628 src = BOOT_SOURCE_RESERVED;
631 val = rcw_src & RCW_SRC_TYPE_MASK;
632 if (val == RCW_SRC_NOR_VAL) {
633 val = rcw_src & NOR_TYPE_MASK;
638 src = BOOT_SOURCE_IFC_NOR;
641 src = BOOT_SOURCE_RESERVED;
644 /* RCW SRC Serial Flash */
645 val = rcw_src & RCW_SRC_SERIAL_MASK;
647 case RCW_SRC_QSPI_VAL:
648 /* RCW SRC Serial NOR (QSPI) */
649 src = BOOT_SOURCE_QSPI_NOR;
651 case RCW_SRC_SD_CARD_VAL:
652 /* RCW SRC SD Card */
653 src = BOOT_SOURCE_SD_MMC;
655 case RCW_SRC_EMMC_VAL:
657 src = BOOT_SOURCE_SD_MMC2;
659 case RCW_SRC_I2C1_VAL:
660 /* RCW SRC I2C1 Extended */
661 src = BOOT_SOURCE_I2C1_EXTENDED;
664 src = BOOT_SOURCE_RESERVED;
668 #elif defined(CONFIG_FSL_LSCH2)
670 val = rcw_src & RCW_SRC_NAND_MASK;
671 if (val == RCW_SRC_NAND_VAL) {
672 val = rcw_src & NAND_RESERVED_MASK;
673 if (val != NAND_RESERVED_1 && val != NAND_RESERVED_2)
674 src = BOOT_SOURCE_IFC_NAND;
678 val = rcw_src & RCW_SRC_NOR_MASK;
679 if (val == NOR_8B_VAL || val == NOR_16B_VAL) {
680 src = BOOT_SOURCE_IFC_NOR;
685 src = BOOT_SOURCE_QSPI_NOR;
688 src = BOOT_SOURCE_SD_MMC;
691 src = BOOT_SOURCE_RESERVED;
697 if (CONFIG_IS_ENABLED(SYS_FSL_ERRATUM_A010539) && !rcw_src)
698 src = BOOT_SOURCE_QSPI_NOR;
700 debug("%s: src 0x%x\n", __func__, src);
704 enum boot_src get_boot_src(void)
709 #if defined(CONFIG_FSL_LSCH3)
710 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
711 #elif defined(CONFIG_FSL_LSCH2)
712 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
715 if (current_el() == 2) {
716 regs.regs[0] = SIP_SVC_RCW;
720 porsr1 = regs.regs[1];
723 if (current_el() == 3 || !porsr1) {
724 #ifdef CONFIG_FSL_LSCH3
725 porsr1 = in_le32(dcfg_ccsr + DCFG_PORSR1 / 4);
726 #elif defined(CONFIG_FSL_LSCH2)
727 porsr1 = in_be32(&gur->porsr1);
731 debug("%s: porsr1 0x%x\n", __func__, porsr1);
733 return __get_boot_src(porsr1);
736 #ifdef CONFIG_ENV_IS_IN_MMC
737 int mmc_get_env_dev(void)
739 enum boot_src src = get_boot_src();
740 int dev = CONFIG_SYS_MMC_ENV_DEV;
743 case BOOT_SOURCE_SD_MMC:
746 case BOOT_SOURCE_SD_MMC2:
757 enum env_location env_get_location(enum env_operation op, int prio)
759 enum boot_src src = get_boot_src();
760 enum env_location env_loc = ENVL_NOWHERE;
765 #ifdef CONFIG_CHAIN_OF_TRUST
767 * If Boot Mode is Secure, return ENVL_NOWHERE
769 if (fsl_check_boot_mode_secure() == 1)
774 case BOOT_SOURCE_IFC_NOR:
775 env_loc = ENVL_FLASH;
777 case BOOT_SOURCE_QSPI_NOR:
779 case BOOT_SOURCE_XSPI_NOR:
780 env_loc = ENVL_SPI_FLASH;
782 case BOOT_SOURCE_IFC_NAND:
784 case BOOT_SOURCE_QSPI_NAND:
786 case BOOT_SOURCE_XSPI_NAND:
789 case BOOT_SOURCE_SD_MMC:
791 case BOOT_SOURCE_SD_MMC2:
794 case BOOT_SOURCE_I2C1_EXTENDED:
800 #ifdef CONFIG_CHAIN_OF_TRUST
805 #endif /* CONFIG_TFABOOT */
807 u32 initiator_type(u32 cluster, int init_id)
809 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
810 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
813 type = gur_in32(&gur->tp_ityp[idx]);
814 if (type & TP_ITYP_AV)
820 u32 cpu_pos_mask(void)
822 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
824 u32 cluster, type, mask = 0;
829 cluster = gur_in32(&gur->tp_cluster[i].lower);
830 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
831 type = initiator_type(cluster, j);
832 if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
833 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
836 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
843 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
844 int i = 0, count = 0;
845 u32 cluster, type, mask = 0;
850 cluster = gur_in32(&gur->tp_cluster[i].lower);
851 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
852 type = initiator_type(cluster, j);
854 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
860 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
866 * Return the number of cores on this SOC.
868 int cpu_numcores(void)
870 return hweight32(cpu_mask());
873 int fsl_qoriq_core_to_cluster(unsigned int core)
875 struct ccsr_gur __iomem *gur =
876 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
877 int i = 0, count = 0;
883 cluster = gur_in32(&gur->tp_cluster[i].lower);
884 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
885 if (initiator_type(cluster, j)) {
892 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
894 return -1; /* cannot identify the cluster */
897 u32 fsl_qoriq_core_to_type(unsigned int core)
899 struct ccsr_gur __iomem *gur =
900 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
901 int i = 0, count = 0;
907 cluster = gur_in32(&gur->tp_cluster[i].lower);
908 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
909 type = initiator_type(cluster, j);
917 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
919 return -1; /* cannot identify the cluster */
922 #ifndef CONFIG_FSL_LSCH3
925 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
927 return gur_in32(&gur->svr);
931 #ifdef CONFIG_DISPLAY_CPUINFO
932 int print_cpuinfo(void)
934 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
935 struct sys_info sysinfo;
937 unsigned int i, core;
938 u32 type, rcw, svr = gur_in32(&gur->svr);
943 printf(" %s (0x%x)\n", buf, svr);
944 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
945 get_sys_info(&sysinfo);
946 puts("Clock Configuration:");
947 for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
950 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
951 printf("CPU%d(%s):%-4s MHz ", core,
952 type == TY_ITYP_VER_A7 ? "A7 " :
953 (type == TY_ITYP_VER_A53 ? "A53" :
954 (type == TY_ITYP_VER_A57 ? "A57" :
955 (type == TY_ITYP_VER_A72 ? "A72" : " "))),
956 strmhz(buf, sysinfo.freq_processor[core]));
958 /* Display platform clock as Bus frequency. */
959 printf("\n Bus: %-4s MHz ",
960 strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
961 printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
962 #ifdef CONFIG_SYS_DPAA_FMAN
963 printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
965 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
966 if (soc_has_dp_ddr()) {
967 printf(" DP-DDR: %-4s MT/s",
968 strmhz(buf, sysinfo.freq_ddrbus2));
974 * Display the RCW, so that no one gets confused as to what RCW
975 * we're actually using for this boot.
977 puts("Reset Configuration Word (RCW):");
978 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
979 rcw = gur_in32(&gur->rcwsr[i]);
981 printf("\n %08x:", i * 4);
982 printf(" %08x", rcw);
990 #ifdef CONFIG_FSL_ESDHC
991 int cpu_mmc_init(bd_t *bis)
993 return fsl_esdhc_mmc_init(bis);
997 int cpu_eth_init(bd_t *bis)
1001 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1002 error = fsl_mc_ldpaa_init(bis);
1004 #ifdef CONFIG_FMAN_ENET
1005 fm_standard_init(bis);
1010 static inline int check_psci(void)
1012 unsigned int psci_ver;
1014 psci_ver = sec_firmware_support_psci_version();
1015 if (psci_ver == PSCI_INVALID_VER)
1021 static void config_core_prefetch(void)
1024 char buffer[HWCONFIG_BUFFER_SIZE];
1025 const char *prefetch_arg = NULL;
1028 struct pt_regs regs;
1030 if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
1033 prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
1037 mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
1039 printf("Core0 prefetch can't be disabled\n");
1043 #define SIP_PREFETCH_DISABLE_64 0xC200FF13
1044 regs.regs[0] = SIP_PREFETCH_DISABLE_64;
1045 regs.regs[1] = mask;
1049 printf("Prefetch disable config failed for mask ");
1051 printf("Prefetch disable config passed for mask ");
1052 printf("0x%x\n", mask);
1056 int arch_early_init_r(void)
1058 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
1061 * erratum A009635 is valid only for LS2080A SoC and
1062 * its personalitiesi
1064 svr_dev_id = get_svr();
1065 if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1068 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
1069 erratum_a009942_check_cpo();
1072 debug("PSCI: PSCI does not exist.\n");
1074 /* if PSCI does not exist, boot secondary cores here */
1075 if (fsl_layerscape_wake_seconday_cores())
1076 printf("Did not wake secondary cores\n");
1079 #ifdef CONFIG_SYS_FSL_HAS_RGMII
1083 config_core_prefetch();
1085 #ifdef CONFIG_SYS_HAS_SERDES
1088 #ifdef CONFIG_FMAN_ENET
1091 #ifdef CONFIG_SYS_DPAA_QBMAN
1092 setup_qbman_portals();
1097 int timer_init(void)
1099 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
1100 #ifdef CONFIG_FSL_LSCH3
1101 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
1103 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
1104 u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
1107 #ifdef COUNTER_FREQUENCY_REAL
1108 unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
1110 /* Update with accurate clock frequency */
1111 if (current_el() == 3)
1112 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
1115 #ifdef CONFIG_FSL_LSCH3
1116 /* Enable timebase for all clusters.
1117 * It is safe to do so even some clusters are not enabled.
1119 out_le32(cltbenr, 0xf);
1122 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
1124 * In certain Layerscape SoCs, the clock for each core's
1125 * has an enable bit in the PMU Physical Core Time Base Enable
1126 * Register (PCTBENR), which allows the watchdog to operate.
1128 setbits_le32(pctbenr, 0xff);
1130 * For LS2080A SoC and its personalities, timer controller
1131 * offset is different
1133 svr_dev_id = get_svr();
1134 if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
1135 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
1139 /* Enable clock for timer
1140 * This is a global setting.
1142 out_le32(cntcr, 0x1);
1147 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
1149 void __efi_runtime reset_cpu(ulong addr)
1153 /* Raise RESET_REQ_B */
1154 val = scfg_in32(rstcr);
1156 scfg_out32(rstcr, val);
1159 #ifdef CONFIG_EFI_LOADER
1161 void __efi_runtime EFIAPI efi_reset_system(
1162 enum efi_reset_type reset_type,
1163 efi_status_t reset_status,
1164 unsigned long data_size, void *reset_data)
1166 switch (reset_type) {
1167 case EFI_RESET_COLD:
1168 case EFI_RESET_WARM:
1169 case EFI_RESET_PLATFORM_SPECIFIC:
1172 case EFI_RESET_SHUTDOWN:
1173 /* Nothing we can do */
1180 efi_status_t efi_reset_system_init(void)
1182 return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
1188 * Calculate reserved memory with given memory bank
1189 * Return aligned memory size on success
1190 * Return (ram_size + needed size) for failure
1192 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
1194 phys_size_t ram_top = ram_size;
1196 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1197 ram_top = mc_get_dram_block_size();
1198 if (ram_top > ram_size)
1199 return ram_size + ram_top;
1201 ram_top = ram_size - ram_top;
1202 /* The start address of MC reserved memory needs to be aligned. */
1203 ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
1206 return ram_size - ram_top;
1209 phys_size_t get_effective_memsize(void)
1211 phys_size_t ea_size, rem = 0;
1214 * For ARMv8 SoCs, DDR memory is split into two or three regions. The
1215 * first region is 2GB space at 0x8000_0000. Secure memory needs to
1216 * allocated from first region. If the memory extends to the second
1217 * region (or the third region if applicable), Management Complex (MC)
1218 * memory should be put into the highest region, i.e. the end of DDR
1219 * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
1220 * U-Boot doesn't relocate itself into higher address. Should DDR be
1221 * configured to skip the first region, this function needs to be
1224 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
1225 ea_size = CONFIG_MAX_MEM_MAPPED;
1226 rem = gd->ram_size - ea_size;
1228 ea_size = gd->ram_size;
1231 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1232 /* Check if we have enough space for secure memory */
1233 if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
1234 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1236 printf("Error: No enough space for secure memory.\n");
1238 /* Check if we have enough memory for MC */
1239 if (rem < board_reserve_ram_top(rem)) {
1240 /* Not enough memory in high region to reserve */
1241 if (ea_size > board_reserve_ram_top(ea_size))
1242 ea_size -= board_reserve_ram_top(ea_size);
1244 printf("Error: No enough space for reserved memory.\n");
1250 #ifdef CONFIG_TFABOOT
1251 phys_size_t tfa_get_dram_size(void)
1253 struct pt_regs regs;
1254 phys_size_t dram_size = 0;
1256 regs.regs[0] = SMC_DRAM_BANK_INFO;
1263 dram_size = regs.regs[1];
1267 static int tfa_dram_init_banksize(void)
1270 struct pt_regs regs;
1271 phys_size_t dram_size = tfa_get_dram_size();
1273 debug("dram_size %llx\n", dram_size);
1279 regs.regs[0] = SMC_DRAM_BANK_INFO;
1288 debug("bank[%d]: start %lx, size %lx\n", i, regs.regs[1],
1290 gd->bd->bi_dram[i].start = regs.regs[1];
1291 gd->bd->bi_dram[i].size = regs.regs[2];
1293 dram_size -= gd->bd->bi_dram[i].size;
1296 } while (dram_size);
1301 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1302 /* Assign memory for MC */
1303 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1304 if (gd->bd->bi_dram[2].size >=
1305 board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1306 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1307 gd->bd->bi_dram[2].size -
1308 board_reserve_ram_top(gd->bd->bi_dram[2].size);
1312 if (gd->bd->bi_dram[1].size >=
1313 board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1314 gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1315 gd->bd->bi_dram[1].size -
1316 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1317 } else if (gd->bd->bi_dram[0].size >
1318 board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1319 gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1320 gd->bd->bi_dram[0].size -
1321 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1324 #endif /* CONFIG_FSL_MC_ENET */
1330 int dram_init_banksize(void)
1332 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1333 phys_size_t dp_ddr_size;
1336 #ifdef CONFIG_TFABOOT
1337 if (!tfa_dram_init_banksize())
1341 * gd->ram_size has the total size of DDR memory, less reserved secure
1342 * memory. The DDR extends from low region to high region(s) presuming
1343 * no hole is created with DDR configuration. gd->arch.secure_ram tracks
1344 * the location of secure memory. gd->arch.resv_ram tracks the location
1345 * of reserved memory for Management Complex (MC). Because gd->ram_size
1346 * is reduced by this function if secure memory is reserved, checking
1347 * gd->arch.secure_ram should be done to avoid running it repeatedly.
1350 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1351 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
1352 debug("No need to run again, skip %s\n", __func__);
1358 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
1359 if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
1360 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
1361 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
1362 gd->bd->bi_dram[1].size = gd->ram_size -
1363 CONFIG_SYS_DDR_BLOCK1_SIZE;
1364 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1365 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
1366 gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
1367 gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
1368 CONFIG_SYS_DDR_BLOCK2_SIZE;
1369 gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
1373 gd->bd->bi_dram[0].size = gd->ram_size;
1375 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1376 if (gd->bd->bi_dram[0].size >
1377 CONFIG_SYS_MEM_RESERVE_SECURE) {
1378 gd->bd->bi_dram[0].size -=
1379 CONFIG_SYS_MEM_RESERVE_SECURE;
1380 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
1381 gd->bd->bi_dram[0].size;
1382 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
1383 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1385 #endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
1387 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1388 /* Assign memory for MC */
1389 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1390 if (gd->bd->bi_dram[2].size >=
1391 board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1392 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1393 gd->bd->bi_dram[2].size -
1394 board_reserve_ram_top(gd->bd->bi_dram[2].size);
1398 if (gd->bd->bi_dram[1].size >=
1399 board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1400 gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1401 gd->bd->bi_dram[1].size -
1402 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1403 } else if (gd->bd->bi_dram[0].size >
1404 board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1405 gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1406 gd->bd->bi_dram[0].size -
1407 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1410 #endif /* CONFIG_FSL_MC_ENET */
1412 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1413 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1414 #error "This SoC shouldn't have DP DDR"
1416 if (soc_has_dp_ddr()) {
1417 /* initialize DP-DDR here */
1420 * DDR controller use 0 as the base address for binding.
1421 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
1423 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
1425 CONFIG_DP_DDR_NUM_CTRLS,
1426 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
1429 gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
1430 gd->bd->bi_dram[2].size = dp_ddr_size;
1432 puts("Not detected");
1437 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1438 debug("%s is called. gd->ram_size is reduced to %lu\n",
1439 __func__, (ulong)gd->ram_size);
1445 #if CONFIG_IS_ENABLED(EFI_LOADER)
1446 void efi_add_known_memory(void)
1449 phys_addr_t ram_start, start;
1450 phys_size_t ram_size;
1454 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
1455 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1456 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1457 #error "This SoC shouldn't have DP DDR"
1460 continue; /* skip DP-DDR */
1462 ram_start = gd->bd->bi_dram[i].start;
1463 ram_size = gd->bd->bi_dram[i].size;
1464 #ifdef CONFIG_RESV_RAM
1465 if (gd->arch.resv_ram >= ram_start &&
1466 gd->arch.resv_ram < ram_start + ram_size)
1467 ram_size = gd->arch.resv_ram - ram_start;
1469 start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
1470 pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
1472 efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY,
1479 * Before DDR size is known, early MMU table have DDR mapped as device memory
1480 * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
1481 * needs to be set for these mappings.
1482 * If a special case configures DDR with holes in the mapping, the holes need
1483 * to be marked as invalid. This is not implemented in this function.
1485 void update_early_mmu_table(void)
1487 if (!gd->arch.tlb_addr)
1490 if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
1491 mmu_change_region_attr(
1492 CONFIG_SYS_SDRAM_BASE,
1494 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1495 PTE_BLOCK_OUTER_SHARE |
1499 mmu_change_region_attr(
1500 CONFIG_SYS_SDRAM_BASE,
1501 CONFIG_SYS_DDR_BLOCK1_SIZE,
1502 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1503 PTE_BLOCK_OUTER_SHARE |
1506 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1507 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
1508 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
1510 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
1511 CONFIG_SYS_DDR_BLOCK2_SIZE) {
1512 mmu_change_region_attr(
1513 CONFIG_SYS_DDR_BLOCK2_BASE,
1514 CONFIG_SYS_DDR_BLOCK2_SIZE,
1515 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1516 PTE_BLOCK_OUTER_SHARE |
1519 mmu_change_region_attr(
1520 CONFIG_SYS_DDR_BLOCK3_BASE,
1522 CONFIG_SYS_DDR_BLOCK1_SIZE -
1523 CONFIG_SYS_DDR_BLOCK2_SIZE,
1524 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1525 PTE_BLOCK_OUTER_SHARE |
1531 mmu_change_region_attr(
1532 CONFIG_SYS_DDR_BLOCK2_BASE,
1534 CONFIG_SYS_DDR_BLOCK1_SIZE,
1535 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1536 PTE_BLOCK_OUTER_SHARE |
1543 __weak int dram_init(void)
1546 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
1547 defined(CONFIG_SPL_BUILD)
1548 /* This will break-before-make MMU for DDR */
1549 update_early_mmu_table();