1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
8 #include <fsl_ddr_sdram.h>
10 #include <linux/errno.h>
11 #include <asm/system.h>
13 #include <asm/armv8/mmu.h>
15 #include <asm/arch/fsl_serdes.h>
16 #include <asm/arch/soc.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/speed.h>
19 #include <fsl_immap.h>
20 #include <asm/arch/mp.h>
21 #include <efi_loader.h>
22 #include <fsl-mc/fsl_mc.h>
23 #ifdef CONFIG_FSL_ESDHC
24 #include <fsl_esdhc.h>
26 #include <asm/armv8/sec_firmware.h>
27 #ifdef CONFIG_SYS_FSL_DDR
30 #include <asm/arch/clock.h>
32 #include <fsl_qbman.h>
34 DECLARE_GLOBAL_DATA_PTR;
36 static struct cpu_type cpu_type_list[] = {
37 CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
38 CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
39 CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
40 CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
41 CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
42 CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
43 CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
44 CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
45 CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
46 CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
47 CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
48 CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
49 CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
50 CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
51 CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
52 CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
53 CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
54 CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
55 CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
58 #define EARLY_PGTABLE_SIZE 0x5000
59 static struct mm_region early_map[] = {
60 #ifdef CONFIG_FSL_LSCH3
61 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
62 CONFIG_SYS_FSL_CCSR_SIZE,
63 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
64 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
66 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
67 SYS_FSL_OCRAM_SPACE_SIZE,
68 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
70 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
71 CONFIG_SYS_FSL_QSPI_SIZE1,
72 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
74 /* For IFC Region #1, only the first 4MB is cache-enabled */
75 { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
76 CONFIG_SYS_FSL_IFC_SIZE1_1,
77 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
79 { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
80 CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
81 CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
82 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
84 { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
85 CONFIG_SYS_FSL_IFC_SIZE1,
86 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
89 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
90 CONFIG_SYS_FSL_DRAM_SIZE1,
91 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
92 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
93 #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
94 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
96 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
99 /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
100 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
101 CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
102 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
105 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
106 CONFIG_SYS_FSL_DCSR_SIZE,
107 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
108 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
110 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
111 CONFIG_SYS_FSL_DRAM_SIZE2,
112 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
113 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
115 #elif defined(CONFIG_FSL_LSCH2)
116 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
117 CONFIG_SYS_FSL_CCSR_SIZE,
118 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
119 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
121 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
122 SYS_FSL_OCRAM_SPACE_SIZE,
123 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
125 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
126 CONFIG_SYS_FSL_DCSR_SIZE,
127 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
128 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
130 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
131 CONFIG_SYS_FSL_QSPI_SIZE,
132 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
134 #ifdef CONFIG_FSL_IFC
135 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
136 CONFIG_SYS_FSL_IFC_SIZE,
137 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
140 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
141 CONFIG_SYS_FSL_DRAM_SIZE1,
142 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
143 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
144 #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
145 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
147 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
149 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
150 CONFIG_SYS_FSL_DRAM_SIZE2,
151 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
152 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
155 {}, /* list terminator */
158 static struct mm_region final_map[] = {
159 #ifdef CONFIG_FSL_LSCH3
160 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
161 CONFIG_SYS_FSL_CCSR_SIZE,
162 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
163 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
165 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
166 SYS_FSL_OCRAM_SPACE_SIZE,
167 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
169 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
170 CONFIG_SYS_FSL_DRAM_SIZE1,
171 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
172 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
174 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
175 CONFIG_SYS_FSL_QSPI_SIZE1,
176 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
177 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
179 { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
180 CONFIG_SYS_FSL_QSPI_SIZE2,
181 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
182 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
184 #ifdef CONFIG_FSL_IFC
185 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
186 CONFIG_SYS_FSL_IFC_SIZE2,
187 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
188 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
191 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
192 CONFIG_SYS_FSL_DCSR_SIZE,
193 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
194 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
196 { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
197 CONFIG_SYS_FSL_MC_SIZE,
198 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
199 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
201 { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
202 CONFIG_SYS_FSL_NI_SIZE,
203 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
204 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
206 /* For QBMAN portal, only the first 64MB is cache-enabled */
207 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
208 CONFIG_SYS_FSL_QBMAN_SIZE_1,
209 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
210 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
212 { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
213 CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
214 CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
215 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
216 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
218 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
219 CONFIG_SYS_PCIE1_PHYS_SIZE,
220 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
221 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
223 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
224 CONFIG_SYS_PCIE2_PHYS_SIZE,
225 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
226 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
228 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
229 CONFIG_SYS_PCIE3_PHYS_SIZE,
230 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
231 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
233 #ifdef CONFIG_ARCH_LS2080A
234 { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
235 CONFIG_SYS_PCIE4_PHYS_SIZE,
236 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
237 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
240 { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
241 CONFIG_SYS_FSL_WRIOP1_SIZE,
242 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
243 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
245 { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
246 CONFIG_SYS_FSL_AIOP1_SIZE,
247 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
248 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
250 { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
251 CONFIG_SYS_FSL_PEBUF_SIZE,
252 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
253 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
255 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
256 CONFIG_SYS_FSL_DRAM_SIZE2,
257 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
258 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
260 #elif defined(CONFIG_FSL_LSCH2)
261 { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
262 CONFIG_SYS_FSL_BOOTROM_SIZE,
263 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
264 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
266 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
267 CONFIG_SYS_FSL_CCSR_SIZE,
268 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
269 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
271 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
272 SYS_FSL_OCRAM_SPACE_SIZE,
273 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
275 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
276 CONFIG_SYS_FSL_DCSR_SIZE,
277 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
278 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
280 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
281 CONFIG_SYS_FSL_QSPI_SIZE,
282 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
283 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
285 #ifdef CONFIG_FSL_IFC
286 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
287 CONFIG_SYS_FSL_IFC_SIZE,
288 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
291 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
292 CONFIG_SYS_FSL_DRAM_SIZE1,
293 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
294 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
296 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
297 CONFIG_SYS_FSL_QBMAN_SIZE,
298 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
299 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
301 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
302 CONFIG_SYS_FSL_DRAM_SIZE2,
303 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
304 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
306 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
307 CONFIG_SYS_PCIE1_PHYS_SIZE,
308 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
309 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
311 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
312 CONFIG_SYS_PCIE2_PHYS_SIZE,
313 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
314 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
316 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
317 CONFIG_SYS_PCIE3_PHYS_SIZE,
318 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
319 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
321 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
322 CONFIG_SYS_FSL_DRAM_SIZE3,
323 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
324 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
327 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
328 {}, /* space holder for secure mem */
333 struct mm_region *mem_map = early_map;
335 void cpu_name(char *name)
337 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
338 unsigned int i, svr, ver;
340 svr = gur_in32(&gur->svr);
341 ver = SVR_SOC_VER(svr);
343 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
344 if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
345 strcpy(name, cpu_type_list[i].name);
347 if (IS_E_PROCESSOR(svr))
350 sprintf(name + strlen(name), " Rev%d.%d",
351 SVR_MAJ(svr), SVR_MIN(svr));
355 if (i == ARRAY_SIZE(cpu_type_list))
356 strcpy(name, "unknown");
359 #ifndef CONFIG_SYS_DCACHE_OFF
361 * To start MMU before DDR is available, we create MMU table in SRAM.
362 * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
363 * levels of translation tables here to cover 40-bit address space.
364 * We use 4KB granule size, with 40 bits physical address, T0SZ=24
365 * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
366 * Note, the debug print in cache_v8.c is not usable for debugging
367 * these early MMU tables because UART is not yet available.
369 static inline void early_mmu_setup(void)
371 unsigned int el = current_el();
373 /* global data is already setup, no allocation yet */
375 gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
377 gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
378 gd->arch.tlb_fillptr = gd->arch.tlb_addr;
379 gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
381 /* Create early page tables */
384 /* point TTBR to the new table */
385 set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
386 get_tcr(el, NULL, NULL) &
387 ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
390 set_sctlr(get_sctlr() | CR_M);
393 static void fix_pcie_mmu_map(void)
395 #ifdef CONFIG_ARCH_LS2080A
398 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
400 svr = gur_in32(&gur->svr);
401 ver = SVR_SOC_VER(svr);
403 /* Fix PCIE base and size for LS2088A */
404 if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
405 (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
406 (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
407 for (i = 0; i < ARRAY_SIZE(final_map); i++) {
408 switch (final_map[i].phys) {
409 case CONFIG_SYS_PCIE1_PHYS_ADDR:
410 final_map[i].phys = 0x2000000000ULL;
411 final_map[i].virt = 0x2000000000ULL;
412 final_map[i].size = 0x800000000ULL;
414 case CONFIG_SYS_PCIE2_PHYS_ADDR:
415 final_map[i].phys = 0x2800000000ULL;
416 final_map[i].virt = 0x2800000000ULL;
417 final_map[i].size = 0x800000000ULL;
419 case CONFIG_SYS_PCIE3_PHYS_ADDR:
420 final_map[i].phys = 0x3000000000ULL;
421 final_map[i].virt = 0x3000000000ULL;
422 final_map[i].size = 0x800000000ULL;
424 case CONFIG_SYS_PCIE4_PHYS_ADDR:
425 final_map[i].phys = 0x3800000000ULL;
426 final_map[i].virt = 0x3800000000ULL;
427 final_map[i].size = 0x800000000ULL;
438 * The final tables look similar to early tables, but different in detail.
439 * These tables are in DRAM. Sub tables are added to enable cache for
442 * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
443 * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
445 static inline void final_mmu_setup(void)
447 u64 tlb_addr_save = gd->arch.tlb_addr;
448 unsigned int el = current_el();
451 /* fix the final_map before filling in the block entries */
456 /* Update mapping for DDR to actual size */
457 for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
459 * Find the entry for DDR mapping and update the address and
460 * size. Zero-sized mapping will be skipped when creating MMU
463 switch (final_map[index].virt) {
464 case CONFIG_SYS_FSL_DRAM_BASE1:
465 final_map[index].virt = gd->bd->bi_dram[0].start;
466 final_map[index].phys = gd->bd->bi_dram[0].start;
467 final_map[index].size = gd->bd->bi_dram[0].size;
469 #ifdef CONFIG_SYS_FSL_DRAM_BASE2
470 case CONFIG_SYS_FSL_DRAM_BASE2:
471 #if (CONFIG_NR_DRAM_BANKS >= 2)
472 final_map[index].virt = gd->bd->bi_dram[1].start;
473 final_map[index].phys = gd->bd->bi_dram[1].start;
474 final_map[index].size = gd->bd->bi_dram[1].size;
476 final_map[index].size = 0;
480 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
481 case CONFIG_SYS_FSL_DRAM_BASE3:
482 #if (CONFIG_NR_DRAM_BANKS >= 3)
483 final_map[index].virt = gd->bd->bi_dram[2].start;
484 final_map[index].phys = gd->bd->bi_dram[2].start;
485 final_map[index].size = gd->bd->bi_dram[2].size;
487 final_map[index].size = 0;
496 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
497 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
500 * Only use gd->arch.secure_ram if the address is
501 * recalculated. Align to 4KB for MMU table.
503 /* put page tables in secure ram */
504 index = ARRAY_SIZE(final_map) - 2;
505 gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
506 final_map[index].virt = gd->arch.secure_ram & ~0x3;
507 final_map[index].phys = final_map[index].virt;
508 final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
509 final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
510 gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
511 tlb_addr_save = gd->arch.tlb_addr;
513 /* Use allocated (board_f.c) memory for TLB */
514 tlb_addr_save = gd->arch.tlb_allocated;
515 gd->arch.tlb_addr = tlb_addr_save;
520 /* Reset the fill ptr */
521 gd->arch.tlb_fillptr = tlb_addr_save;
523 /* Create normal system page tables */
526 /* Create emergency page tables */
527 gd->arch.tlb_addr = gd->arch.tlb_fillptr;
528 gd->arch.tlb_emerg = gd->arch.tlb_addr;
530 gd->arch.tlb_addr = tlb_addr_save;
532 /* Disable cache and MMU */
533 dcache_disable(); /* TLBs are invalidated */
534 invalidate_icache_all();
536 /* point TTBR to the new table */
537 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
540 set_sctlr(get_sctlr() | CR_M);
543 u64 get_page_table_size(void)
548 int arch_cpu_init(void)
551 * This function is called before U-Boot relocates itself to speed up
552 * on system running. It is not necessary to run if performance is not
553 * critical. Skip if MMU is already enabled by SPL or other means.
555 if (get_sctlr() & CR_M)
559 __asm_invalidate_dcache_all();
560 __asm_invalidate_tlb_all();
562 set_sctlr(get_sctlr() | CR_C);
572 * This function is called from common/board_r.c.
573 * It recreates MMU table in main memory.
575 void enable_caches(void)
578 __asm_invalidate_tlb_all();
584 u32 initiator_type(u32 cluster, int init_id)
586 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
587 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
590 type = gur_in32(&gur->tp_ityp[idx]);
591 if (type & TP_ITYP_AV)
597 u32 cpu_pos_mask(void)
599 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
601 u32 cluster, type, mask = 0;
606 cluster = gur_in32(&gur->tp_cluster[i].lower);
607 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
608 type = initiator_type(cluster, j);
609 if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
610 mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
613 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
620 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
621 int i = 0, count = 0;
622 u32 cluster, type, mask = 0;
627 cluster = gur_in32(&gur->tp_cluster[i].lower);
628 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
629 type = initiator_type(cluster, j);
631 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
637 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
643 * Return the number of cores on this SOC.
645 int cpu_numcores(void)
647 return hweight32(cpu_mask());
650 int fsl_qoriq_core_to_cluster(unsigned int core)
652 struct ccsr_gur __iomem *gur =
653 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
654 int i = 0, count = 0;
660 cluster = gur_in32(&gur->tp_cluster[i].lower);
661 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
662 if (initiator_type(cluster, j)) {
669 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
671 return -1; /* cannot identify the cluster */
674 u32 fsl_qoriq_core_to_type(unsigned int core)
676 struct ccsr_gur __iomem *gur =
677 (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
678 int i = 0, count = 0;
684 cluster = gur_in32(&gur->tp_cluster[i].lower);
685 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
686 type = initiator_type(cluster, j);
694 } while ((cluster & TP_CLUSTER_EOC) == 0x0);
696 return -1; /* cannot identify the cluster */
699 #ifndef CONFIG_FSL_LSCH3
702 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
704 return gur_in32(&gur->svr);
708 #ifdef CONFIG_DISPLAY_CPUINFO
709 int print_cpuinfo(void)
711 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
712 struct sys_info sysinfo;
714 unsigned int i, core;
715 u32 type, rcw, svr = gur_in32(&gur->svr);
720 printf(" %s (0x%x)\n", buf, svr);
721 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
722 get_sys_info(&sysinfo);
723 puts("Clock Configuration:");
724 for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
727 type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
728 printf("CPU%d(%s):%-4s MHz ", core,
729 type == TY_ITYP_VER_A7 ? "A7 " :
730 (type == TY_ITYP_VER_A53 ? "A53" :
731 (type == TY_ITYP_VER_A57 ? "A57" :
732 (type == TY_ITYP_VER_A72 ? "A72" : " "))),
733 strmhz(buf, sysinfo.freq_processor[core]));
735 /* Display platform clock as Bus frequency. */
736 printf("\n Bus: %-4s MHz ",
737 strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
738 printf("DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
739 #ifdef CONFIG_SYS_DPAA_FMAN
740 printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
742 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
743 if (soc_has_dp_ddr()) {
744 printf(" DP-DDR: %-4s MT/s",
745 strmhz(buf, sysinfo.freq_ddrbus2));
751 * Display the RCW, so that no one gets confused as to what RCW
752 * we're actually using for this boot.
754 puts("Reset Configuration Word (RCW):");
755 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
756 rcw = gur_in32(&gur->rcwsr[i]);
758 printf("\n %08x:", i * 4);
759 printf(" %08x", rcw);
767 #ifdef CONFIG_FSL_ESDHC
768 int cpu_mmc_init(bd_t *bis)
770 return fsl_esdhc_mmc_init(bis);
774 int cpu_eth_init(bd_t *bis)
778 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
779 error = fsl_mc_ldpaa_init(bis);
781 #ifdef CONFIG_FMAN_ENET
782 fm_standard_init(bis);
787 static inline int check_psci(void)
789 unsigned int psci_ver;
791 psci_ver = sec_firmware_support_psci_version();
792 if (psci_ver == PSCI_INVALID_VER)
798 static void config_core_prefetch(void)
801 char buffer[HWCONFIG_BUFFER_SIZE];
802 const char *prefetch_arg = NULL;
807 if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
810 prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
814 mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
816 printf("Core0 prefetch can't be disabled\n");
820 #define SIP_PREFETCH_DISABLE_64 0xC200FF13
821 regs.regs[0] = SIP_PREFETCH_DISABLE_64;
826 printf("Prefetch disable config failed for mask ");
828 printf("Prefetch disable config passed for mask ");
829 printf("0x%x\n", mask);
833 int arch_early_init_r(void)
835 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
838 * erratum A009635 is valid only for LS2080A SoC and
841 svr_dev_id = get_svr();
842 if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
845 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
846 erratum_a009942_check_cpo();
849 debug("PSCI: PSCI does not exist.\n");
851 /* if PSCI does not exist, boot secondary cores here */
852 if (fsl_layerscape_wake_seconday_cores())
853 printf("Did not wake secondary cores\n");
856 #ifdef CONFIG_SYS_FSL_HAS_RGMII
860 config_core_prefetch();
862 #ifdef CONFIG_SYS_HAS_SERDES
865 #ifdef CONFIG_FMAN_ENET
868 #ifdef CONFIG_SYS_DPAA_QBMAN
869 setup_qbman_portals();
876 u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
877 #ifdef CONFIG_FSL_LSCH3
878 u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
880 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
881 u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
884 #ifdef COUNTER_FREQUENCY_REAL
885 unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
887 /* Update with accurate clock frequency */
888 if (current_el() == 3)
889 asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
892 #ifdef CONFIG_FSL_LSCH3
893 /* Enable timebase for all clusters.
894 * It is safe to do so even some clusters are not enabled.
896 out_le32(cltbenr, 0xf);
899 #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
901 * In certain Layerscape SoCs, the clock for each core's
902 * has an enable bit in the PMU Physical Core Time Base Enable
903 * Register (PCTBENR), which allows the watchdog to operate.
905 setbits_le32(pctbenr, 0xff);
907 * For LS2080A SoC and its personalities, timer controller
908 * offset is different
910 svr_dev_id = get_svr();
911 if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
912 cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
916 /* Enable clock for timer
917 * This is a global setting.
919 out_le32(cntcr, 0x1);
924 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
926 void __efi_runtime reset_cpu(ulong addr)
930 /* Raise RESET_REQ_B */
931 val = scfg_in32(rstcr);
933 scfg_out32(rstcr, val);
936 #ifdef CONFIG_EFI_LOADER
938 void __efi_runtime EFIAPI efi_reset_system(
939 enum efi_reset_type reset_type,
940 efi_status_t reset_status,
941 unsigned long data_size, void *reset_data)
943 switch (reset_type) {
946 case EFI_RESET_PLATFORM_SPECIFIC:
949 case EFI_RESET_SHUTDOWN:
950 /* Nothing we can do */
957 efi_status_t efi_reset_system_init(void)
959 return efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
965 * Calculate reserved memory with given memory bank
966 * Return aligned memory size on success
967 * Return (ram_size + needed size) for failure
969 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
971 phys_size_t ram_top = ram_size;
973 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
974 ram_top = mc_get_dram_block_size();
975 if (ram_top > ram_size)
976 return ram_size + ram_top;
978 ram_top = ram_size - ram_top;
979 /* The start address of MC reserved memory needs to be aligned. */
980 ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
983 return ram_size - ram_top;
986 phys_size_t get_effective_memsize(void)
988 phys_size_t ea_size, rem = 0;
991 * For ARMv8 SoCs, DDR memory is split into two or three regions. The
992 * first region is 2GB space at 0x8000_0000. Secure memory needs to
993 * allocated from first region. If the memory extends to the second
994 * region (or the third region if applicable), Management Complex (MC)
995 * memory should be put into the highest region, i.e. the end of DDR
996 * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
997 * U-Boot doesn't relocate itself into higher address. Should DDR be
998 * configured to skip the first region, this function needs to be
1001 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
1002 ea_size = CONFIG_MAX_MEM_MAPPED;
1003 rem = gd->ram_size - ea_size;
1005 ea_size = gd->ram_size;
1008 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1009 /* Check if we have enough space for secure memory */
1010 if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
1011 ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1013 printf("Error: No enough space for secure memory.\n");
1015 /* Check if we have enough memory for MC */
1016 if (rem < board_reserve_ram_top(rem)) {
1017 /* Not enough memory in high region to reserve */
1018 if (ea_size > board_reserve_ram_top(ea_size))
1019 ea_size -= board_reserve_ram_top(ea_size);
1021 printf("Error: No enough space for reserved memory.\n");
1027 int dram_init_banksize(void)
1029 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1030 phys_size_t dp_ddr_size;
1034 * gd->ram_size has the total size of DDR memory, less reserved secure
1035 * memory. The DDR extends from low region to high region(s) presuming
1036 * no hole is created with DDR configuration. gd->arch.secure_ram tracks
1037 * the location of secure memory. gd->arch.resv_ram tracks the location
1038 * of reserved memory for Management Complex (MC). Because gd->ram_size
1039 * is reduced by this function if secure memory is reserved, checking
1040 * gd->arch.secure_ram should be done to avoid running it repeatedly.
1043 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1044 if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
1045 debug("No need to run again, skip %s\n", __func__);
1051 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
1052 if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
1053 gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
1054 gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
1055 gd->bd->bi_dram[1].size = gd->ram_size -
1056 CONFIG_SYS_DDR_BLOCK1_SIZE;
1057 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1058 if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
1059 gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
1060 gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
1061 CONFIG_SYS_DDR_BLOCK2_SIZE;
1062 gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
1066 gd->bd->bi_dram[0].size = gd->ram_size;
1068 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1069 if (gd->bd->bi_dram[0].size >
1070 CONFIG_SYS_MEM_RESERVE_SECURE) {
1071 gd->bd->bi_dram[0].size -=
1072 CONFIG_SYS_MEM_RESERVE_SECURE;
1073 gd->arch.secure_ram = gd->bd->bi_dram[0].start +
1074 gd->bd->bi_dram[0].size;
1075 gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
1076 gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
1078 #endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
1080 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
1081 /* Assign memory for MC */
1082 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1083 if (gd->bd->bi_dram[2].size >=
1084 board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
1085 gd->arch.resv_ram = gd->bd->bi_dram[2].start +
1086 gd->bd->bi_dram[2].size -
1087 board_reserve_ram_top(gd->bd->bi_dram[2].size);
1091 if (gd->bd->bi_dram[1].size >=
1092 board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
1093 gd->arch.resv_ram = gd->bd->bi_dram[1].start +
1094 gd->bd->bi_dram[1].size -
1095 board_reserve_ram_top(gd->bd->bi_dram[1].size);
1096 } else if (gd->bd->bi_dram[0].size >
1097 board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
1098 gd->arch.resv_ram = gd->bd->bi_dram[0].start +
1099 gd->bd->bi_dram[0].size -
1100 board_reserve_ram_top(gd->bd->bi_dram[0].size);
1103 #endif /* CONFIG_FSL_MC_ENET */
1105 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1106 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1107 #error "This SoC shouldn't have DP DDR"
1109 if (soc_has_dp_ddr()) {
1110 /* initialize DP-DDR here */
1113 * DDR controller use 0 as the base address for binding.
1114 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
1116 dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
1118 CONFIG_DP_DDR_NUM_CTRLS,
1119 CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
1122 gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
1123 gd->bd->bi_dram[2].size = dp_ddr_size;
1125 puts("Not detected");
1130 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
1131 debug("%s is called. gd->ram_size is reduced to %lu\n",
1132 __func__, (ulong)gd->ram_size);
1138 #if CONFIG_IS_ENABLED(EFI_LOADER)
1139 void efi_add_known_memory(void)
1142 phys_addr_t ram_start, start;
1143 phys_size_t ram_size;
1147 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
1148 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
1149 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1150 #error "This SoC shouldn't have DP DDR"
1153 continue; /* skip DP-DDR */
1155 ram_start = gd->bd->bi_dram[i].start;
1156 ram_size = gd->bd->bi_dram[i].size;
1157 #ifdef CONFIG_RESV_RAM
1158 if (gd->arch.resv_ram >= ram_start &&
1159 gd->arch.resv_ram < ram_start + ram_size)
1160 ram_size = gd->arch.resv_ram - ram_start;
1162 start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
1163 pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
1165 efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY,
1172 * Before DDR size is known, early MMU table have DDR mapped as device memory
1173 * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
1174 * needs to be set for these mappings.
1175 * If a special case configures DDR with holes in the mapping, the holes need
1176 * to be marked as invalid. This is not implemented in this function.
1178 void update_early_mmu_table(void)
1180 if (!gd->arch.tlb_addr)
1183 if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
1184 mmu_change_region_attr(
1185 CONFIG_SYS_SDRAM_BASE,
1187 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1188 PTE_BLOCK_OUTER_SHARE |
1192 mmu_change_region_attr(
1193 CONFIG_SYS_SDRAM_BASE,
1194 CONFIG_SYS_DDR_BLOCK1_SIZE,
1195 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1196 PTE_BLOCK_OUTER_SHARE |
1199 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
1200 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
1201 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
1203 if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
1204 CONFIG_SYS_DDR_BLOCK2_SIZE) {
1205 mmu_change_region_attr(
1206 CONFIG_SYS_DDR_BLOCK2_BASE,
1207 CONFIG_SYS_DDR_BLOCK2_SIZE,
1208 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1209 PTE_BLOCK_OUTER_SHARE |
1212 mmu_change_region_attr(
1213 CONFIG_SYS_DDR_BLOCK3_BASE,
1215 CONFIG_SYS_DDR_BLOCK1_SIZE -
1216 CONFIG_SYS_DDR_BLOCK2_SIZE,
1217 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1218 PTE_BLOCK_OUTER_SHARE |
1224 mmu_change_region_attr(
1225 CONFIG_SYS_DDR_BLOCK2_BASE,
1227 CONFIG_SYS_DDR_BLOCK1_SIZE,
1228 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
1229 PTE_BLOCK_OUTER_SHARE |
1236 __weak int dram_init(void)
1239 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
1240 /* This will break-before-make MMU for DDR */
1241 update_early_mmu_table();