6 select SYS_FSL_ERRATUM_A010315
12 select SYS_FSL_DDR_VER_50
13 select SYS_FSL_ERRATUM_A010315
14 select SYS_FSL_ERRATUM_A010539
21 select SYS_FSL_DDR_VER_50
22 select SYS_FSL_ERRATUM_A010539
30 select SYS_FSL_DDR_VER_50
31 select SYS_FSL_HAS_DP_DDR
44 menu "Layerscape architecture"
45 depends on FSL_LSCH2 || FSL_LSCH3
50 config SYS_FSL_ERRATUM_A010315
51 bool "Workaround for PCIe erratum A010315"
53 config SYS_FSL_ERRATUM_A010539
54 bool "Workaround for PIN MUX erratum A010539"
57 int "Maximum number of CPUs permitted for Layerscape"
58 default 4 if ARCH_LS1043A
59 default 4 if ARCH_LS1046A
60 default 16 if ARCH_LS2080A
63 Set this number to the maximum number of possible CPUs in the SoC.
64 SoCs may have multiple clusters with each cluster may have multiple
65 ports. If some ports are reserved but higher ports are used for
66 cores, count the reserved ports. This will allocate enough memory
67 in spin table to properly handle all cores.
69 config NUM_DDR_CONTROLLERS
70 int "Maximum DDR controllers"
71 default 3 if ARCH_LS2080A
77 Enable Freescale Secure Boot feature
79 config SYS_FSL_IFC_BANK_COUNT
80 int "Maximum banks of Integrated flash controller"
81 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
82 default 4 if ARCH_LS1043A
83 default 4 if ARCH_LS1046A
84 default 8 if ARCH_LS2080A
86 config SYS_FSL_HAS_DP_DDR
99 bool "Freescale DDR driver"
101 Select Freescale General DDR driver, shared between most Freescale
102 PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
103 based Layerscape SoCs (such as ls2080a).
105 config SYS_FSL_DDR_BE
108 Access DDR registers in big-endian.
110 config SYS_FSL_DDR_LE
113 Access DDR registers in little-endian.
115 config SYS_FSL_DDR_VER
117 default 50 if SYS_FSL_DDR_VER_50
119 config SYS_FSL_DDR_VER_50
122 config SYS_FSL_DDRC_ARM_GEN3
125 config SYS_FSL_DDRC_GEN4
129 bool "Freescale DDR3 controller"
130 depends on !SYS_FSL_DDR4
132 select SYS_FSL_DDRC_ARM_GEN3
134 Enable Freescale DDR3 controller on ARM-based SoCs.
137 bool "Freescale DDR4 controller"
139 select SYS_FSL_DDRC_GEN4
141 Enable Freescale DDR4 controller.