4 select ARM_ERRATA_855873
10 select SYS_FSL_ERRATUM_A010315
11 select SYS_FSL_ERRATUM_A009798
12 select SYS_FSL_ERRATUM_A008997
13 select SYS_FSL_ERRATUM_A009007
14 select SYS_FSL_ERRATUM_A009008
15 select ARCH_EARLY_INIT_R
16 select BOARD_EARLY_INIT_F
18 select SYS_I2C_MXC_I2C1
19 select SYS_I2C_MXC_I2C2
24 select ARMV8_SET_SMPEN
25 select ARM_ERRATA_855873
31 select SYS_FSL_DDR_VER_50
32 select SYS_FSL_ERRATUM_A008850
33 select SYS_FSL_ERRATUM_A008997
34 select SYS_FSL_ERRATUM_A009007
35 select SYS_FSL_ERRATUM_A009008
36 select SYS_FSL_ERRATUM_A009660
37 select SYS_FSL_ERRATUM_A009663
38 select SYS_FSL_ERRATUM_A009798
39 select SYS_FSL_ERRATUM_A009929
40 select SYS_FSL_ERRATUM_A009942
41 select SYS_FSL_ERRATUM_A010315
42 select SYS_FSL_ERRATUM_A010539
43 select SYS_FSL_HAS_DDR3
44 select SYS_FSL_HAS_DDR4
45 select ARCH_EARLY_INIT_R
46 select BOARD_EARLY_INIT_F
48 select SYS_I2C_MXC_I2C1
49 select SYS_I2C_MXC_I2C2
50 select SYS_I2C_MXC_I2C3
51 select SYS_I2C_MXC_I2C4
58 select ARMV8_SET_SMPEN
64 select SYS_FSL_DDR_VER_50
65 select SYS_FSL_ERRATUM_A008336
66 select SYS_FSL_ERRATUM_A008511
67 select SYS_FSL_ERRATUM_A008850
68 select SYS_FSL_ERRATUM_A008997
69 select SYS_FSL_ERRATUM_A009007
70 select SYS_FSL_ERRATUM_A009008
71 select SYS_FSL_ERRATUM_A009798
72 select SYS_FSL_ERRATUM_A009801
73 select SYS_FSL_ERRATUM_A009803
74 select SYS_FSL_ERRATUM_A009942
75 select SYS_FSL_ERRATUM_A010165
76 select SYS_FSL_ERRATUM_A010539
77 select SYS_FSL_HAS_DDR4
79 select ARCH_EARLY_INIT_R
80 select BOARD_EARLY_INIT_F
82 select SYS_I2C_MXC_I2C1
83 select SYS_I2C_MXC_I2C2
84 select SYS_I2C_MXC_I2C3
85 select SYS_I2C_MXC_I2C4
91 select ARMV8_SET_SMPEN
92 select ARM_ERRATA_855873
98 select SYS_FSL_DDR_VER_50
101 select SYS_FSL_ERRATUM_A009803
102 select SYS_FSL_ERRATUM_A009942
103 select SYS_FSL_ERRATUM_A010165
104 select SYS_FSL_ERRATUM_A008511
105 select SYS_FSL_ERRATUM_A008850
106 select SYS_FSL_ERRATUM_A009007
107 select SYS_FSL_HAS_CCI400
108 select SYS_FSL_HAS_DDR4
109 select SYS_FSL_HAS_RGMII
110 select SYS_FSL_HAS_SEC
111 select SYS_FSL_SEC_COMPAT_5
112 select SYS_FSL_SEC_LE
113 select SYS_FSL_SRDS_1
114 select SYS_FSL_SRDS_2
116 select ARCH_EARLY_INIT_R
117 select BOARD_EARLY_INIT_F
119 select SYS_I2C_MXC_I2C1
120 select SYS_I2C_MXC_I2C2
121 select SYS_I2C_MXC_I2C3
122 select SYS_I2C_MXC_I2C4
128 select ARMV8_SET_SMPEN
129 select ARM_ERRATA_826974
130 select ARM_ERRATA_828024
131 select ARM_ERRATA_829520
132 select ARM_ERRATA_833471
134 select SYS_FSL_SRDS_1
135 select SYS_HAS_SERDES
137 select SYS_FSL_DDR_LE
138 select SYS_FSL_DDR_VER_50
139 select SYS_FSL_HAS_CCN504
140 select SYS_FSL_HAS_DP_DDR
141 select SYS_FSL_HAS_SEC
142 select SYS_FSL_HAS_DDR4
143 select SYS_FSL_SEC_COMPAT_5
144 select SYS_FSL_SEC_LE
145 select SYS_FSL_SRDS_2
148 select SYS_FSL_ERRATUM_A008336
149 select SYS_FSL_ERRATUM_A008511
150 select SYS_FSL_ERRATUM_A008514
151 select SYS_FSL_ERRATUM_A008585
152 select SYS_FSL_ERRATUM_A008997
153 select SYS_FSL_ERRATUM_A009007
154 select SYS_FSL_ERRATUM_A009008
155 select SYS_FSL_ERRATUM_A009635
156 select SYS_FSL_ERRATUM_A009663
157 select SYS_FSL_ERRATUM_A009798
158 select SYS_FSL_ERRATUM_A009801
159 select SYS_FSL_ERRATUM_A009803
160 select SYS_FSL_ERRATUM_A009942
161 select SYS_FSL_ERRATUM_A010165
162 select SYS_FSL_ERRATUM_A009203
163 select ARCH_EARLY_INIT_R
164 select BOARD_EARLY_INIT_F
166 select SYS_I2C_MXC_I2C1
167 select SYS_I2C_MXC_I2C2
168 select SYS_I2C_MXC_I2C3
169 select SYS_I2C_MXC_I2C4
174 select SYS_FSL_HAS_CCI400
175 select SYS_FSL_HAS_SEC
176 select SYS_FSL_SEC_COMPAT_5
177 select SYS_FSL_SEC_BE
183 bool "Management Complex network"
184 depends on ARCH_LS2080A || ARCH_LS1088A
188 Enable Management Complex (MC) network
190 menu "Layerscape architecture"
191 depends on FSL_LSCH2 || FSL_LSCH3
193 config FSL_PCIE_COMPAT
194 string "PCIe compatible of Kernel DT"
195 depends on PCIE_LAYERSCAPE
196 default "fsl,ls1012a-pcie" if ARCH_LS1012A
197 default "fsl,ls1043a-pcie" if ARCH_LS1043A
198 default "fsl,ls1046a-pcie" if ARCH_LS1046A
199 default "fsl,ls2080a-pcie" if ARCH_LS2080A
200 default "fsl,ls1088a-pcie" if ARCH_LS1088A
202 This compatible is used to find pci controller node in Kernel DT
205 config HAS_FEATURE_GIC64K_ALIGN
207 default y if ARCH_LS1043A
209 config HAS_FEATURE_ENHANCED_MSI
211 default y if ARCH_LS1043A
213 menu "Layerscape PPA"
215 bool "FSL Layerscape PPA firmware support"
216 depends on !ARMV8_PSCI
217 select ARMV8_SEC_FIRMWARE_SUPPORT
218 select SEC_FIRMWARE_ARMV8_PSCI
219 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
221 The FSL Primary Protected Application (PPA) is a software component
222 which is loaded during boot stage, and then remains resident in RAM
223 and runs in the TrustZone after boot.
226 config SPL_FSL_LS_PPA
227 bool "FSL Layerscape PPA firmware support for SPL build"
228 depends on !ARMV8_PSCI
229 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
230 select SEC_FIRMWARE_ARMV8_PSCI
231 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
233 The FSL Primary Protected Application (PPA) is a software component
234 which is loaded during boot stage, and then remains resident in RAM
235 and runs in the TrustZone after boot. This is to load PPA during SPL
236 stage instead of the RAM version of U-Boot. Once PPA is initialized,
237 the rest of U-Boot (including RAM version) runs at EL2.
239 prompt "FSL Layerscape PPA firmware loading-media select"
240 depends on FSL_LS_PPA
241 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
242 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
243 default SYS_LS_PPA_FW_IN_XIP
245 config SYS_LS_PPA_FW_IN_XIP
248 Say Y here if the PPA firmware locate at XIP flash, such
249 as NOR or QSPI flash.
251 config SYS_LS_PPA_FW_IN_MMC
252 bool "eMMC or SD Card"
254 Say Y here if the PPA firmware locate at eMMC/SD card.
256 config SYS_LS_PPA_FW_IN_NAND
259 Say Y here if the PPA firmware locate at NAND flash.
263 config SYS_LS_PPA_FW_ADDR
264 hex "Address of PPA firmware loading from"
265 depends on FSL_LS_PPA
266 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
267 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
268 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
269 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A
270 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
271 default 0x400000 if SYS_LS_PPA_FW_IN_MMC
272 default 0x400000 if SYS_LS_PPA_FW_IN_NAND
275 If the PPA firmware locate at XIP flash, such as NOR or
276 QSPI flash, this address is a directly memory-mapped.
277 If it is in a serial accessed flash, such as NAND and SD
278 card, it is a byte offset.
280 config SYS_LS_PPA_ESBC_ADDR
281 hex "hdr address of PPA firmware loading from"
282 depends on FSL_LS_PPA && CHAIN_OF_TRUST
283 default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
284 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
285 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
286 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
287 default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
288 default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1088A
289 default 0x680000 if SYS_LS_PPA_FW_IN_MMC
290 default 0x680000 if SYS_LS_PPA_FW_IN_NAND
292 If the PPA header firmware locate at XIP flash, such as NOR or
293 QSPI flash, this address is a directly memory-mapped.
294 If it is in a serial accessed flash, such as NAND and SD
295 card, it is a byte offset.
297 config LS_PPA_ESBC_HDR_SIZE
298 hex "Length of PPA ESBC header"
299 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
302 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
303 NAND to memory to validate PPA image.
307 config SYS_FSL_ERRATUM_A008997
308 bool "Workaround for USB PHY erratum A008997"
310 config SYS_FSL_ERRATUM_A009007
313 Workaround for USB PHY erratum A009007
315 config SYS_FSL_ERRATUM_A009008
316 bool "Workaround for USB PHY erratum A009008"
318 config SYS_FSL_ERRATUM_A009798
319 bool "Workaround for USB PHY erratum A009798"
321 config SYS_FSL_ERRATUM_A010315
322 bool "Workaround for PCIe erratum A010315"
324 config SYS_FSL_ERRATUM_A010539
325 bool "Workaround for PIN MUX erratum A010539"
328 int "Maximum number of CPUs permitted for Layerscape"
329 default 4 if ARCH_LS1043A
330 default 4 if ARCH_LS1046A
331 default 16 if ARCH_LS2080A
332 default 8 if ARCH_LS1088A
335 Set this number to the maximum number of possible CPUs in the SoC.
336 SoCs may have multiple clusters with each cluster may have multiple
337 ports. If some ports are reserved but higher ports are used for
338 cores, count the reserved ports. This will allocate enough memory
339 in spin table to properly handle all cores.
344 Enable Freescale Secure Boot feature
347 bool "Init the QSPI AHB bus"
349 The default setting for QSPI AHB bus just support 3bytes addressing.
350 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
351 bus for those flashes to support the full QSPI flash size.
353 config SYS_CCI400_OFFSET
354 hex "Offset for CCI400 base"
355 depends on SYS_FSL_HAS_CCI400
356 default 0x3090000 if ARCH_LS1088A
357 default 0x180000 if FSL_LSCH2
359 Offset for CCI400 base
360 CCI400 base addr = CCSRBAR + CCI400_OFFSET
362 config SYS_FSL_IFC_BANK_COUNT
363 int "Maximum banks of Integrated flash controller"
364 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
365 default 4 if ARCH_LS1043A
366 default 4 if ARCH_LS1046A
367 default 8 if ARCH_LS2080A || ARCH_LS1088A
369 config SYS_FSL_HAS_CCI400
372 config SYS_FSL_HAS_CCN504
375 config SYS_FSL_HAS_DP_DDR
378 config SYS_FSL_SRDS_1
381 config SYS_FSL_SRDS_2
384 config SYS_HAS_SERDES
395 menu "Layerscape clock tree configuration"
396 depends on FSL_LSCH2 || FSL_LSCH3
399 bool "Enable clock tree initialization"
402 config CLUSTER_CLK_FREQ
403 int "Reference clock of core cluster"
404 depends on ARCH_LS1012A
407 This number is the reference clock frequency of core PLL.
408 For most platforms, the core PLL and Platform PLL have the same
409 reference clock, but for some platforms, LS1012A for instance,
410 they are provided sepatately.
412 config SYS_FSL_PCLK_DIV
413 int "Platform clock divider"
414 default 1 if ARCH_LS1043A
415 default 1 if ARCH_LS1046A
416 default 1 if ARCH_LS1088A
419 This is the divider that is used to derive Platform clock from
420 Platform PLL, in another word:
421 Platform_clk = Platform_PLL_freq / this_divider
423 config SYS_FSL_DSPI_CLK_DIV
424 int "DSPI clock divider"
425 default 1 if ARCH_LS1043A
428 This is the divider that is used to derive DSPI clock from Platform
429 clock, in another word DSPI_clk = Platform_clk / this_divider.
431 config SYS_FSL_DUART_CLK_DIV
432 int "DUART clock divider"
433 default 1 if ARCH_LS1043A
436 This is the divider that is used to derive DUART clock from Platform
437 clock, in another word DUART_clk = Platform_clk / this_divider.
439 config SYS_FSL_I2C_CLK_DIV
440 int "I2C clock divider"
441 default 1 if ARCH_LS1043A
444 This is the divider that is used to derive I2C clock from Platform
445 clock, in another word I2C_clk = Platform_clk / this_divider.
447 config SYS_FSL_IFC_CLK_DIV
448 int "IFC clock divider"
449 default 1 if ARCH_LS1043A
452 This is the divider that is used to derive IFC clock from Platform
453 clock, in another word IFC_clk = Platform_clk / this_divider.
455 config SYS_FSL_LPUART_CLK_DIV
456 int "LPUART clock divider"
457 default 1 if ARCH_LS1043A
460 This is the divider that is used to derive LPUART clock from Platform
461 clock, in another word LPUART_clk = Platform_clk / this_divider.
463 config SYS_FSL_SDHC_CLK_DIV
464 int "SDHC clock divider"
465 default 1 if ARCH_LS1043A
466 default 1 if ARCH_LS1012A
469 This is the divider that is used to derive SDHC clock from Platform
470 clock, in another word SDHC_clk = Platform_clk / this_divider.
476 Reserve memory from the top, tracked by gd->arch.resv_ram. This
477 reserved RAM can be used by special driver that resides in memory
478 after U-Boot exits. It's up to implementation to allocate and allow
479 access to this reserved memory. For example, the reserved RAM can
480 be at the high end of physical memory. The reserve RAM may be
481 excluded from memory bank(s) passed to OS, or marked as reserved.
486 Ethernet controller 1, this is connected to MAC3.
487 Provides DPAA2 capabilities
492 Ethernet controller 2, this is connected to MAC4.
493 Provides DPAA2 capabilities
495 config SYS_FSL_ERRATUM_A008336
498 config SYS_FSL_ERRATUM_A008514
501 config SYS_FSL_ERRATUM_A008585
504 config SYS_FSL_ERRATUM_A008850
507 config SYS_FSL_ERRATUM_A009203
510 config SYS_FSL_ERRATUM_A009635
513 config SYS_FSL_ERRATUM_A009660
516 config SYS_FSL_ERRATUM_A009929
520 config SYS_FSL_HAS_RGMII
522 depends on SYS_FSL_EC1 || SYS_FSL_EC2
525 config SYS_MC_RSV_MEM_ALIGN
526 hex "Management Complex reserved memory alignment"
528 default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A
530 Reserved memory needs to be aligned for MC to use. Default value
534 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
536 config HAS_FSL_XHCI_USB
538 default y if ARCH_LS1043A || ARCH_LS1046A
540 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
541 pins, select it when the pins are assigned to USB.