7 select SYS_FSL_ERRATUM_A010315
8 select ARCH_EARLY_INIT_R
9 select BOARD_EARLY_INIT_F
13 select ARMV8_SET_SMPEN
17 select SYS_FSL_DDR_VER_50
18 select SYS_FSL_ERRATUM_A008850
19 select SYS_FSL_ERRATUM_A009660
20 select SYS_FSL_ERRATUM_A009663
21 select SYS_FSL_ERRATUM_A009929
22 select SYS_FSL_ERRATUM_A009942
23 select SYS_FSL_ERRATUM_A010315
24 select SYS_FSL_ERRATUM_A010539
25 select SYS_FSL_HAS_DDR3
26 select SYS_FSL_HAS_DDR4
27 select ARCH_EARLY_INIT_R
28 select BOARD_EARLY_INIT_F
34 select ARMV8_SET_SMPEN
38 select SYS_FSL_DDR_VER_50
39 select SYS_FSL_ERRATUM_A008336
40 select SYS_FSL_ERRATUM_A008511
41 select SYS_FSL_ERRATUM_A008850
42 select SYS_FSL_ERRATUM_A009801
43 select SYS_FSL_ERRATUM_A009803
44 select SYS_FSL_ERRATUM_A009942
45 select SYS_FSL_ERRATUM_A010165
46 select SYS_FSL_ERRATUM_A010539
47 select SYS_FSL_HAS_DDR4
49 select ARCH_EARLY_INIT_R
50 select BOARD_EARLY_INIT_F
55 select ARMV8_SET_SMPEN
56 select ARM_ERRATA_826974
57 select ARM_ERRATA_828024
58 select ARM_ERRATA_829520
59 select ARM_ERRATA_833471
63 select SYS_FSL_DDR_VER_50
64 select SYS_FSL_HAS_DP_DDR
65 select SYS_FSL_HAS_SEC
66 select SYS_FSL_HAS_DDR4
67 select SYS_FSL_SEC_COMPAT_5
72 select SYS_FSL_ERRATUM_A008336
73 select SYS_FSL_ERRATUM_A008511
74 select SYS_FSL_ERRATUM_A008514
75 select SYS_FSL_ERRATUM_A008585
76 select SYS_FSL_ERRATUM_A009635
77 select SYS_FSL_ERRATUM_A009663
78 select SYS_FSL_ERRATUM_A009801
79 select SYS_FSL_ERRATUM_A009803
80 select SYS_FSL_ERRATUM_A009942
81 select SYS_FSL_ERRATUM_A010165
82 select SYS_FSL_ERRATUM_A009203
83 select ARCH_EARLY_INIT_R
84 select BOARD_EARLY_INIT_F
88 select SYS_FSL_HAS_CCI400
89 select SYS_FSL_HAS_SEC
90 select SYS_FSL_SEC_COMPAT_5
101 bool "Management Complex network"
102 depends on ARCH_LS2080A
106 Enable Management Complex (MC) network
108 menu "Layerscape architecture"
109 depends on FSL_LSCH2 || FSL_LSCH3
111 config FSL_PCIE_COMPAT
112 string "PCIe compatible of Kernel DT"
113 depends on PCIE_LAYERSCAPE
114 default "fsl,ls1012a-pcie" if ARCH_LS1012A
115 default "fsl,ls1043a-pcie" if ARCH_LS1043A
116 default "fsl,ls1046a-pcie" if ARCH_LS1046A
117 default "fsl,ls2080a-pcie" if ARCH_LS2080A
119 This compatible is used to find pci controller node in Kernel DT
122 config HAS_FEATURE_GIC64K_ALIGN
124 default y if ARCH_LS1043A
126 config HAS_FEATURE_ENHANCED_MSI
128 default y if ARCH_LS1043A
130 menu "Layerscape PPA"
132 bool "FSL Layerscape PPA firmware support"
133 depends on !ARMV8_PSCI
134 select ARMV8_SEC_FIRMWARE_SUPPORT
135 select SEC_FIRMWARE_ARMV8_PSCI
136 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
138 The FSL Primary Protected Application (PPA) is a software component
139 which is loaded during boot stage, and then remains resident in RAM
140 and runs in the TrustZone after boot.
143 config SPL_FSL_LS_PPA
144 bool "FSL Layerscape PPA firmware support for SPL build"
145 depends on !ARMV8_PSCI
146 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
147 select SEC_FIRMWARE_ARMV8_PSCI
148 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
150 The FSL Primary Protected Application (PPA) is a software component
151 which is loaded during boot stage, and then remains resident in RAM
152 and runs in the TrustZone after boot. This is to load PPA during SPL
153 stage instead of the RAM version of U-Boot. Once PPA is initialized,
154 the rest of U-Boot (including RAM version) runs at EL2.
156 prompt "FSL Layerscape PPA firmware loading-media select"
157 depends on FSL_LS_PPA
158 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
159 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
160 default SYS_LS_PPA_FW_IN_XIP
162 config SYS_LS_PPA_FW_IN_XIP
165 Say Y here if the PPA firmware locate at XIP flash, such
166 as NOR or QSPI flash.
168 config SYS_LS_PPA_FW_IN_MMC
169 bool "eMMC or SD Card"
171 Say Y here if the PPA firmware locate at eMMC/SD card.
173 config SYS_LS_PPA_FW_IN_NAND
176 Say Y here if the PPA firmware locate at NAND flash.
180 config SYS_LS_PPA_FW_ADDR
181 hex "Address of PPA firmware loading from"
182 depends on FSL_LS_PPA
183 default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
184 default 0x40400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
185 default 0x580400000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
186 default 0x60400000 if SYS_LS_PPA_FW_IN_XIP
187 default 0x400000 if SYS_LS_PPA_FW_IN_MMC
188 default 0x400000 if SYS_LS_PPA_FW_IN_NAND
191 If the PPA firmware locate at XIP flash, such as NOR or
192 QSPI flash, this address is a directly memory-mapped.
193 If it is in a serial accessed flash, such as NAND and SD
194 card, it is a byte offset.
196 config SYS_LS_PPA_ESBC_ADDR
197 hex "hdr address of PPA firmware loading from"
198 depends on FSL_LS_PPA && CHAIN_OF_TRUST
199 default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
200 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
201 default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
202 default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
203 default 0x680000 if SYS_LS_PPA_FW_IN_MMC
204 default 0x680000 if SYS_LS_PPA_FW_IN_NAND
206 If the PPA header firmware locate at XIP flash, such as NOR or
207 QSPI flash, this address is a directly memory-mapped.
208 If it is in a serial accessed flash, such as NAND and SD
209 card, it is a byte offset.
211 config LS_PPA_ESBC_HDR_SIZE
212 hex "Length of PPA ESBC header"
213 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
216 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
217 NAND to memory to validate PPA image.
221 config SYS_FSL_ERRATUM_A010315
222 bool "Workaround for PCIe erratum A010315"
224 config SYS_FSL_ERRATUM_A010539
225 bool "Workaround for PIN MUX erratum A010539"
228 int "Maximum number of CPUs permitted for Layerscape"
229 default 4 if ARCH_LS1043A
230 default 4 if ARCH_LS1046A
231 default 16 if ARCH_LS2080A
234 Set this number to the maximum number of possible CPUs in the SoC.
235 SoCs may have multiple clusters with each cluster may have multiple
236 ports. If some ports are reserved but higher ports are used for
237 cores, count the reserved ports. This will allocate enough memory
238 in spin table to properly handle all cores.
243 Enable Freescale Secure Boot feature
246 bool "Init the QSPI AHB bus"
248 The default setting for QSPI AHB bus just support 3bytes addressing.
249 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
250 bus for those flashes to support the full QSPI flash size.
252 config SYS_CCI400_OFFSET
253 hex "Offset for CCI400 base"
254 depends on SYS_FSL_HAS_CCI400
255 default 0x3090000 if ARCH_LS1088A
256 default 0x180000 if FSL_LSCH2
258 Offset for CCI400 base
259 CCI400 base addr = CCSRBAR + CCI400_OFFSET
261 config SYS_FSL_IFC_BANK_COUNT
262 int "Maximum banks of Integrated flash controller"
263 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
264 default 4 if ARCH_LS1043A
265 default 4 if ARCH_LS1046A
266 default 8 if ARCH_LS2080A
268 config SYS_FSL_HAS_CCI400
271 config SYS_FSL_HAS_DP_DDR
274 config SYS_FSL_SRDS_1
277 config SYS_FSL_SRDS_2
280 config SYS_HAS_SERDES
291 menu "Layerscape clock tree configuration"
292 depends on FSL_LSCH2 || FSL_LSCH3
295 bool "Enable clock tree initialization"
298 config CLUSTER_CLK_FREQ
299 int "Reference clock of core cluster"
300 depends on ARCH_LS1012A
303 This number is the reference clock frequency of core PLL.
304 For most platforms, the core PLL and Platform PLL have the same
305 reference clock, but for some platforms, LS1012A for instance,
306 they are provided sepatately.
308 config SYS_FSL_PCLK_DIV
309 int "Platform clock divider"
310 default 1 if ARCH_LS1043A
311 default 1 if ARCH_LS1046A
314 This is the divider that is used to derive Platform clock from
315 Platform PLL, in another word:
316 Platform_clk = Platform_PLL_freq / this_divider
318 config SYS_FSL_DSPI_CLK_DIV
319 int "DSPI clock divider"
320 default 1 if ARCH_LS1043A
323 This is the divider that is used to derive DSPI clock from Platform
324 clock, in another word DSPI_clk = Platform_clk / this_divider.
326 config SYS_FSL_DUART_CLK_DIV
327 int "DUART clock divider"
328 default 1 if ARCH_LS1043A
331 This is the divider that is used to derive DUART clock from Platform
332 clock, in another word DUART_clk = Platform_clk / this_divider.
334 config SYS_FSL_I2C_CLK_DIV
335 int "I2C clock divider"
336 default 1 if ARCH_LS1043A
339 This is the divider that is used to derive I2C clock from Platform
340 clock, in another word I2C_clk = Platform_clk / this_divider.
342 config SYS_FSL_IFC_CLK_DIV
343 int "IFC clock divider"
344 default 1 if ARCH_LS1043A
347 This is the divider that is used to derive IFC clock from Platform
348 clock, in another word IFC_clk = Platform_clk / this_divider.
350 config SYS_FSL_LPUART_CLK_DIV
351 int "LPUART clock divider"
352 default 1 if ARCH_LS1043A
355 This is the divider that is used to derive LPUART clock from Platform
356 clock, in another word LPUART_clk = Platform_clk / this_divider.
358 config SYS_FSL_SDHC_CLK_DIV
359 int "SDHC clock divider"
360 default 1 if ARCH_LS1043A
361 default 1 if ARCH_LS1012A
364 This is the divider that is used to derive SDHC clock from Platform
365 clock, in another word SDHC_clk = Platform_clk / this_divider.
371 Reserve memory from the top, tracked by gd->arch.resv_ram. This
372 reserved RAM can be used by special driver that resides in memory
373 after U-Boot exits. It's up to implementation to allocate and allow
374 access to this reserved memory. For example, the reserved RAM can
375 be at the high end of physical memory. The reserve RAM may be
376 excluded from memory bank(s) passed to OS, or marked as reserved.
378 config SYS_FSL_ERRATUM_A008336
381 config SYS_FSL_ERRATUM_A008514
384 config SYS_FSL_ERRATUM_A008585
387 config SYS_FSL_ERRATUM_A008850
390 config SYS_FSL_ERRATUM_A009203
393 config SYS_FSL_ERRATUM_A009635
396 config SYS_FSL_ERRATUM_A009660
399 config SYS_FSL_ERRATUM_A009929
402 config SYS_MC_RSV_MEM_ALIGN
403 hex "Management Complex reserved memory alignment"
407 Reserved memory needs to be aligned for MC to use. Default value
411 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A