4 select ARM_ERRATA_855873 if !TFABOOT
11 select SYS_FSL_ERRATUM_A010315
12 select SYS_FSL_ERRATUM_A009798
13 select SYS_FSL_ERRATUM_A008997
14 select SYS_FSL_ERRATUM_A009007
15 select SYS_FSL_ERRATUM_A009008
16 select ARCH_EARLY_INIT_R
17 select BOARD_EARLY_INIT_F
19 select SYS_I2C_MXC_I2C1
20 select SYS_I2C_MXC_I2C2
25 select ARMV8_SET_SMPEN
28 select SYS_FSL_HAS_CCI400
33 select SYS_FSL_DDR_VER_50
34 select SYS_FSL_HAS_DDR3
35 select SYS_FSL_HAS_DDR4
36 select SYS_FSL_HAS_SEC
37 select SYS_FSL_SEC_COMPAT_5
40 select ARCH_EARLY_INIT_R
41 select BOARD_EARLY_INIT_F
43 select SYS_I2C_MXC_I2C1
44 select SYS_I2C_MXC_I2C2
45 select SYS_I2C_MXC_I2C3
46 select SYS_I2C_MXC_I2C4
47 select SYS_I2C_MXC_I2C5
48 select SYS_I2C_MXC_I2C6
49 select SYS_I2C_MXC_I2C7
50 select SYS_I2C_MXC_I2C8
51 select SYS_FSL_ERRATUM_A008997
52 select SYS_FSL_ERRATUM_A009007
53 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
54 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
55 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
60 select ARMV8_SET_SMPEN
61 select ARM_ERRATA_855873 if !TFABOOT
68 select SYS_FSL_DDR_VER_50
69 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
70 select SYS_FSL_ERRATUM_A008997
71 select SYS_FSL_ERRATUM_A009007
72 select SYS_FSL_ERRATUM_A009008
73 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
74 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
75 select SYS_FSL_ERRATUM_A009798
76 select SYS_FSL_ERRATUM_A009929
77 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
78 select SYS_FSL_ERRATUM_A010315
79 select SYS_FSL_ERRATUM_A010539
80 select SYS_FSL_HAS_DDR3
81 select SYS_FSL_HAS_DDR4
82 select ARCH_EARLY_INIT_R
83 select BOARD_EARLY_INIT_F
85 select SYS_I2C_MXC_I2C1
86 select SYS_I2C_MXC_I2C2
87 select SYS_I2C_MXC_I2C3
88 select SYS_I2C_MXC_I2C4
93 select ARMV8_SET_SMPEN
100 select SYS_FSL_DDR_VER_50
101 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
102 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
103 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
104 select SYS_FSL_ERRATUM_A008997
105 select SYS_FSL_ERRATUM_A009007
106 select SYS_FSL_ERRATUM_A009008
107 select SYS_FSL_ERRATUM_A009798
108 select SYS_FSL_ERRATUM_A009801
109 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
110 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
111 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
112 select SYS_FSL_ERRATUM_A010539
113 select SYS_FSL_HAS_DDR4
114 select SYS_FSL_SRDS_2
115 select ARCH_EARLY_INIT_R
116 select BOARD_EARLY_INIT_F
118 select SYS_I2C_MXC_I2C1
119 select SYS_I2C_MXC_I2C2
120 select SYS_I2C_MXC_I2C3
121 select SYS_I2C_MXC_I2C4
127 select ARMV8_SET_SMPEN
128 select ARM_ERRATA_855873 if !TFABOOT
129 select FSL_LAYERSCAPE
131 select SYS_FSL_SRDS_1
132 select SYS_HAS_SERDES
134 select SYS_FSL_DDR_LE
135 select SYS_FSL_DDR_VER_50
138 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
139 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
140 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
141 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
142 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
143 select SYS_FSL_ERRATUM_A009007
144 select SYS_FSL_HAS_CCI400
145 select SYS_FSL_HAS_DDR4
146 select SYS_FSL_HAS_RGMII
147 select SYS_FSL_HAS_SEC
148 select SYS_FSL_SEC_COMPAT_5
149 select SYS_FSL_SEC_LE
150 select SYS_FSL_SRDS_1
151 select SYS_FSL_SRDS_2
154 select FSL_TZPC_BP147
155 select ARCH_EARLY_INIT_R
156 select BOARD_EARLY_INIT_F
158 select SYS_I2C_MXC_I2C1
159 select SYS_I2C_MXC_I2C2
160 select SYS_I2C_MXC_I2C3
161 select SYS_I2C_MXC_I2C4
167 select ARMV8_SET_SMPEN
168 select ARM_ERRATA_826974
169 select ARM_ERRATA_828024
170 select ARM_ERRATA_829520
171 select ARM_ERRATA_833471
172 select FSL_LAYERSCAPE
174 select SYS_FSL_SRDS_1
175 select SYS_HAS_SERDES
177 select SYS_FSL_DDR_LE
178 select SYS_FSL_DDR_VER_50
179 select SYS_FSL_HAS_CCN504
180 select SYS_FSL_HAS_DP_DDR
181 select SYS_FSL_HAS_SEC
182 select SYS_FSL_HAS_DDR4
183 select SYS_FSL_SEC_COMPAT_5
184 select SYS_FSL_SEC_LE
185 select SYS_FSL_SRDS_2
189 select FSL_TZPC_BP147
190 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
191 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
192 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
193 select SYS_FSL_ERRATUM_A008585
194 select SYS_FSL_ERRATUM_A008997
195 select SYS_FSL_ERRATUM_A009007
196 select SYS_FSL_ERRATUM_A009008
197 select SYS_FSL_ERRATUM_A009635
198 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
199 select SYS_FSL_ERRATUM_A009798
200 select SYS_FSL_ERRATUM_A009801
201 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
202 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
203 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
204 select SYS_FSL_ERRATUM_A009203
205 select ARCH_EARLY_INIT_R
206 select BOARD_EARLY_INIT_F
208 select SYS_I2C_MXC_I2C1
209 select SYS_I2C_MXC_I2C2
210 select SYS_I2C_MXC_I2C3
211 select SYS_I2C_MXC_I2C4
212 imply DISTRO_DEFAULTS
217 select ARMV8_SET_SMPEN
220 select SYS_HAS_SERDES
221 select SYS_FSL_SRDS_1
222 select SYS_FSL_SRDS_2
223 select SYS_NXP_SRDS_3
225 select SYS_FSL_DDR_LE
226 select SYS_FSL_DDR_VER_50
229 select SYS_FSL_HAS_RGMII
230 select SYS_FSL_HAS_SEC
231 select SYS_FSL_HAS_CCN508
232 select SYS_FSL_HAS_DDR4
233 select SYS_FSL_SEC_COMPAT_5
234 select SYS_FSL_SEC_LE
235 select ARCH_EARLY_INIT_R
236 select BOARD_EARLY_INIT_F
238 imply DISTRO_DEFAULTS
245 select SYS_FSL_HAS_CCI400
246 select SYS_FSL_HAS_SEC
247 select SYS_FSL_SEC_COMPAT_5
248 select SYS_FSL_SEC_BE
257 bool "Management Complex network"
258 depends on ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
262 Enable Management Complex (MC) network
264 menu "Layerscape architecture"
265 depends on FSL_LSCH2 || FSL_LSCH3
267 config FSL_LAYERSCAPE
270 config FSL_PCIE_COMPAT
271 string "PCIe compatible of Kernel DT"
272 depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4
273 default "fsl,ls1012a-pcie" if ARCH_LS1012A
274 default "fsl,ls1028a-pcie" if ARCH_LS1028A
275 default "fsl,ls1043a-pcie" if ARCH_LS1043A
276 default "fsl,ls1046a-pcie" if ARCH_LS1046A
277 default "fsl,ls2080a-pcie" if ARCH_LS2080A
278 default "fsl,ls1088a-pcie" if ARCH_LS1088A
279 default "fsl,lx2160a-pcie" if ARCH_LX2160A
281 This compatible is used to find pci controller node in Kernel DT
284 config HAS_FEATURE_GIC64K_ALIGN
286 default y if ARCH_LS1043A
288 config HAS_FEATURE_ENHANCED_MSI
290 default y if ARCH_LS1043A
292 menu "Layerscape PPA"
294 bool "FSL Layerscape PPA firmware support"
295 depends on !ARMV8_PSCI
296 select ARMV8_SEC_FIRMWARE_SUPPORT
297 select SEC_FIRMWARE_ARMV8_PSCI
298 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
300 The FSL Primary Protected Application (PPA) is a software component
301 which is loaded during boot stage, and then remains resident in RAM
302 and runs in the TrustZone after boot.
305 config SPL_FSL_LS_PPA
306 bool "FSL Layerscape PPA firmware support for SPL build"
307 depends on !ARMV8_PSCI
308 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
309 select SEC_FIRMWARE_ARMV8_PSCI
310 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
312 The FSL Primary Protected Application (PPA) is a software component
313 which is loaded during boot stage, and then remains resident in RAM
314 and runs in the TrustZone after boot. This is to load PPA during SPL
315 stage instead of the RAM version of U-Boot. Once PPA is initialized,
316 the rest of U-Boot (including RAM version) runs at EL2.
318 prompt "FSL Layerscape PPA firmware loading-media select"
319 depends on FSL_LS_PPA
320 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
321 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
322 default SYS_LS_PPA_FW_IN_XIP
324 config SYS_LS_PPA_FW_IN_XIP
327 Say Y here if the PPA firmware locate at XIP flash, such
328 as NOR or QSPI flash.
330 config SYS_LS_PPA_FW_IN_MMC
331 bool "eMMC or SD Card"
333 Say Y here if the PPA firmware locate at eMMC/SD card.
335 config SYS_LS_PPA_FW_IN_NAND
338 Say Y here if the PPA firmware locate at NAND flash.
342 config LS_PPA_ESBC_HDR_SIZE
343 hex "Length of PPA ESBC header"
344 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
347 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
348 NAND to memory to validate PPA image.
352 config SYS_FSL_ERRATUM_A008997
353 bool "Workaround for USB PHY erratum A008997"
355 config SYS_FSL_ERRATUM_A009007
358 Workaround for USB PHY erratum A009007
360 config SYS_FSL_ERRATUM_A009008
361 bool "Workaround for USB PHY erratum A009008"
363 config SYS_FSL_ERRATUM_A009798
364 bool "Workaround for USB PHY erratum A009798"
366 config SYS_FSL_ERRATUM_A010315
367 bool "Workaround for PCIe erratum A010315"
369 config SYS_FSL_ERRATUM_A010539
370 bool "Workaround for PIN MUX erratum A010539"
373 int "Maximum number of CPUs permitted for Layerscape"
374 default 2 if ARCH_LS1028A
375 default 4 if ARCH_LS1043A
376 default 4 if ARCH_LS1046A
377 default 16 if ARCH_LS2080A
378 default 8 if ARCH_LS1088A
379 default 16 if ARCH_LX2160A
382 Set this number to the maximum number of possible CPUs in the SoC.
383 SoCs may have multiple clusters with each cluster may have multiple
384 ports. If some ports are reserved but higher ports are used for
385 cores, count the reserved ports. This will allocate enough memory
386 in spin table to properly handle all cores.
389 bool "Fan controller"
391 Enable the EMC2305 fan controller for configuration of fan
397 Enable Freescale Secure Boot feature
400 bool "Init the QSPI AHB bus"
402 The default setting for QSPI AHB bus just support 3bytes addressing.
403 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
404 bus for those flashes to support the full QSPI flash size.
406 config SYS_CCI400_OFFSET
407 hex "Offset for CCI400 base"
408 depends on SYS_FSL_HAS_CCI400
409 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
410 default 0x180000 if FSL_LSCH2
412 Offset for CCI400 base
413 CCI400 base addr = CCSRBAR + CCI400_OFFSET
415 config SYS_FSL_IFC_BANK_COUNT
416 int "Maximum banks of Integrated flash controller"
417 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
418 default 4 if ARCH_LS1043A
419 default 4 if ARCH_LS1046A
420 default 8 if ARCH_LS2080A || ARCH_LS1088A
422 config SYS_FSL_HAS_CCI400
425 config SYS_FSL_HAS_CCN504
428 config SYS_FSL_HAS_CCN508
431 config SYS_FSL_HAS_DP_DDR
434 config SYS_FSL_SRDS_1
437 config SYS_FSL_SRDS_2
440 config SYS_NXP_SRDS_3
443 config SYS_HAS_SERDES
455 config FSL_TZPC_BP147
459 menu "Layerscape clock tree configuration"
460 depends on FSL_LSCH2 || FSL_LSCH3
463 bool "Enable clock tree initialization"
466 config CLUSTER_CLK_FREQ
467 int "Reference clock of core cluster"
468 depends on ARCH_LS1012A
471 This number is the reference clock frequency of core PLL.
472 For most platforms, the core PLL and Platform PLL have the same
473 reference clock, but for some platforms, LS1012A for instance,
474 they are provided sepatately.
476 config SYS_FSL_PCLK_DIV
477 int "Platform clock divider"
478 default 1 if ARCH_LS1028A
479 default 1 if ARCH_LS1043A
480 default 1 if ARCH_LS1046A
481 default 1 if ARCH_LS1088A
484 This is the divider that is used to derive Platform clock from
485 Platform PLL, in another word:
486 Platform_clk = Platform_PLL_freq / this_divider
488 config SYS_FSL_DSPI_CLK_DIV
489 int "DSPI clock divider"
490 default 1 if ARCH_LS1043A
493 This is the divider that is used to derive DSPI clock from Platform
494 clock, in another word DSPI_clk = Platform_clk / this_divider.
496 config SYS_FSL_DUART_CLK_DIV
497 int "DUART clock divider"
498 default 1 if ARCH_LS1043A
499 default 4 if ARCH_LX2160A
502 This is the divider that is used to derive DUART clock from Platform
503 clock, in another word DUART_clk = Platform_clk / this_divider.
505 config SYS_FSL_I2C_CLK_DIV
506 int "I2C clock divider"
507 default 1 if ARCH_LS1043A
510 This is the divider that is used to derive I2C clock from Platform
511 clock, in another word I2C_clk = Platform_clk / this_divider.
513 config SYS_FSL_IFC_CLK_DIV
514 int "IFC clock divider"
515 default 1 if ARCH_LS1043A
518 This is the divider that is used to derive IFC clock from Platform
519 clock, in another word IFC_clk = Platform_clk / this_divider.
521 config SYS_FSL_LPUART_CLK_DIV
522 int "LPUART clock divider"
523 default 1 if ARCH_LS1043A
526 This is the divider that is used to derive LPUART clock from Platform
527 clock, in another word LPUART_clk = Platform_clk / this_divider.
529 config SYS_FSL_SDHC_CLK_DIV
530 int "SDHC clock divider"
531 default 1 if ARCH_LS1043A
532 default 1 if ARCH_LS1012A
535 This is the divider that is used to derive SDHC clock from Platform
536 clock, in another word SDHC_clk = Platform_clk / this_divider.
538 config SYS_FSL_QMAN_CLK_DIV
539 int "QMAN clock divider"
540 default 1 if ARCH_LS1043A
543 This is the divider that is used to derive QMAN clock from Platform
544 clock, in another word QMAN_clk = Platform_clk / this_divider.
550 Reserve memory from the top, tracked by gd->arch.resv_ram. This
551 reserved RAM can be used by special driver that resides in memory
552 after U-Boot exits. It's up to implementation to allocate and allow
553 access to this reserved memory. For example, the reserved RAM can
554 be at the high end of physical memory. The reserve RAM may be
555 excluded from memory bank(s) passed to OS, or marked as reserved.
560 Ethernet controller 1, this is connected to
561 MAC17 for LX2160A or to MAC3 for other SoCs
562 Provides DPAA2 capabilities
567 Ethernet controller 2, this is connected to
568 MAC18 for LX2160A or to MAC4 for other SoCs
569 Provides DPAA2 capabilities
571 config SYS_FSL_ERRATUM_A008336
574 config SYS_FSL_ERRATUM_A008514
577 config SYS_FSL_ERRATUM_A008585
580 config SYS_FSL_ERRATUM_A008850
583 config SYS_FSL_ERRATUM_A009203
586 config SYS_FSL_ERRATUM_A009635
589 config SYS_FSL_ERRATUM_A009660
592 config SYS_FSL_ERRATUM_A009929
596 config SYS_FSL_HAS_RGMII
598 depends on SYS_FSL_EC1 || SYS_FSL_EC2
601 config SYS_MC_RSV_MEM_ALIGN
602 hex "Management Complex reserved memory alignment"
604 default 0x20000000 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LX2160A
606 Reserved memory needs to be aligned for MC to use. Default value
610 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
612 config HAS_FSL_XHCI_USB
614 default y if ARCH_LS1043A || ARCH_LS1046A
616 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
617 pins, select it when the pins are assigned to USB.