4 select ARM_ERRATA_855873 if !TFABOOT
11 select SYS_FSL_ERRATUM_A010315
12 select SYS_FSL_ERRATUM_A009798
13 select SYS_FSL_ERRATUM_A008997
14 select SYS_FSL_ERRATUM_A009007
15 select SYS_FSL_ERRATUM_A009008
16 select ARCH_EARLY_INIT_R
17 select BOARD_EARLY_INIT_F
19 select SYS_I2C_MXC_I2C1
20 select SYS_I2C_MXC_I2C2
25 select ARMV8_SET_SMPEN
28 select SYS_FSL_HAS_CCI400
33 select SYS_FSL_DDR_VER_50
34 select SYS_FSL_HAS_DDR3
35 select SYS_FSL_HAS_DDR4
36 select SYS_FSL_HAS_SEC
37 select SYS_FSL_SEC_COMPAT_5
40 select ARCH_EARLY_INIT_R
41 select BOARD_EARLY_INIT_F
43 select SYS_FSL_ERRATUM_A008997
44 select SYS_FSL_ERRATUM_A009007
45 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
46 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
47 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
52 select ARMV8_SET_SMPEN
53 select ARM_ERRATA_855873 if !TFABOOT
60 select SYS_FSL_DDR_VER_50
61 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
62 select SYS_FSL_ERRATUM_A008997
63 select SYS_FSL_ERRATUM_A009007
64 select SYS_FSL_ERRATUM_A009008
65 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
66 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
67 select SYS_FSL_ERRATUM_A009798
68 select SYS_FSL_ERRATUM_A009929
69 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
70 select SYS_FSL_ERRATUM_A010315
71 select SYS_FSL_ERRATUM_A010539
72 select SYS_FSL_HAS_DDR3
73 select SYS_FSL_HAS_DDR4
74 select ARCH_EARLY_INIT_R
75 select BOARD_EARLY_INIT_F
77 select SYS_I2C_MXC_I2C1
78 select SYS_I2C_MXC_I2C2
79 select SYS_I2C_MXC_I2C3
80 select SYS_I2C_MXC_I2C4
85 select ARMV8_SET_SMPEN
92 select SYS_FSL_DDR_VER_50
93 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
94 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
95 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
96 select SYS_FSL_ERRATUM_A008997
97 select SYS_FSL_ERRATUM_A009007
98 select SYS_FSL_ERRATUM_A009008
99 select SYS_FSL_ERRATUM_A009798
100 select SYS_FSL_ERRATUM_A009801
101 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
102 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
103 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
104 select SYS_FSL_ERRATUM_A010539
105 select SYS_FSL_HAS_DDR4
106 select SYS_FSL_SRDS_2
107 select ARCH_EARLY_INIT_R
108 select BOARD_EARLY_INIT_F
110 select SYS_I2C_MXC_I2C1
111 select SYS_I2C_MXC_I2C2
112 select SYS_I2C_MXC_I2C3
113 select SYS_I2C_MXC_I2C4
119 select ARMV8_SET_SMPEN
120 select ARM_ERRATA_855873 if !TFABOOT
121 select FSL_LAYERSCAPE
123 select SYS_FSL_SRDS_1
124 select SYS_HAS_SERDES
126 select SYS_FSL_DDR_LE
127 select SYS_FSL_DDR_VER_50
130 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
131 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
132 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
133 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
134 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
135 select SYS_FSL_ERRATUM_A009007
136 select SYS_FSL_HAS_CCI400
137 select SYS_FSL_HAS_DDR4
138 select SYS_FSL_HAS_RGMII
139 select SYS_FSL_HAS_SEC
140 select SYS_FSL_SEC_COMPAT_5
141 select SYS_FSL_SEC_LE
142 select SYS_FSL_SRDS_1
143 select SYS_FSL_SRDS_2
146 select FSL_TZPC_BP147
147 select ARCH_EARLY_INIT_R
148 select BOARD_EARLY_INIT_F
150 select SYS_I2C_MXC_I2C1 if !TFABOOT
151 select SYS_I2C_MXC_I2C2 if !TFABOOT
152 select SYS_I2C_MXC_I2C3 if !TFABOOT
153 select SYS_I2C_MXC_I2C4 if !TFABOOT
159 select ARMV8_SET_SMPEN
160 select ARM_ERRATA_826974
161 select ARM_ERRATA_828024
162 select ARM_ERRATA_829520
163 select ARM_ERRATA_833471
164 select FSL_LAYERSCAPE
166 select SYS_FSL_SRDS_1
167 select SYS_HAS_SERDES
169 select SYS_FSL_DDR_LE
170 select SYS_FSL_DDR_VER_50
171 select SYS_FSL_HAS_CCN504
172 select SYS_FSL_HAS_DP_DDR
173 select SYS_FSL_HAS_SEC
174 select SYS_FSL_HAS_DDR4
175 select SYS_FSL_SEC_COMPAT_5
176 select SYS_FSL_SEC_LE
177 select SYS_FSL_SRDS_2
181 select FSL_TZPC_BP147
182 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
183 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
184 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
185 select SYS_FSL_ERRATUM_A008585
186 select SYS_FSL_ERRATUM_A008997
187 select SYS_FSL_ERRATUM_A009007
188 select SYS_FSL_ERRATUM_A009008
189 select SYS_FSL_ERRATUM_A009635
190 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
191 select SYS_FSL_ERRATUM_A009798
192 select SYS_FSL_ERRATUM_A009801
193 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
194 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
195 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
196 select SYS_FSL_ERRATUM_A009203
197 select ARCH_EARLY_INIT_R
198 select BOARD_EARLY_INIT_F
200 select SYS_I2C_MXC_I2C1 if !TFABOOT
201 select SYS_I2C_MXC_I2C2 if !TFABOOT
202 select SYS_I2C_MXC_I2C3 if !TFABOOT
203 select SYS_I2C_MXC_I2C4 if !TFABOOT
204 imply DISTRO_DEFAULTS
209 select ARMV8_SET_SMPEN
212 select SYS_HAS_SERDES
213 select SYS_FSL_SRDS_1
214 select SYS_FSL_SRDS_2
215 select SYS_NXP_SRDS_3
217 select SYS_FSL_DDR_LE
218 select SYS_FSL_DDR_VER_50
221 select SYS_FSL_HAS_RGMII
222 select SYS_FSL_HAS_SEC
223 select SYS_FSL_HAS_CCN508
224 select SYS_FSL_HAS_DDR4
225 select SYS_FSL_SEC_COMPAT_5
226 select SYS_FSL_SEC_LE
227 select ARCH_EARLY_INIT_R
228 select BOARD_EARLY_INIT_F
230 imply DISTRO_DEFAULTS
237 select SYS_FSL_HAS_CCI400
238 select SYS_FSL_HAS_SEC
239 select SYS_FSL_SEC_COMPAT_5
240 select SYS_FSL_SEC_BE
248 menu "Layerscape architecture"
249 depends on FSL_LSCH2 || FSL_LSCH3
251 config FSL_LAYERSCAPE
254 config FSL_PCIE_COMPAT
255 string "PCIe compatible of Kernel DT"
256 depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4
257 default "fsl,ls1012a-pcie" if ARCH_LS1012A
258 default "fsl,ls1028a-pcie" if ARCH_LS1028A
259 default "fsl,ls1043a-pcie" if ARCH_LS1043A
260 default "fsl,ls1046a-pcie" if ARCH_LS1046A
261 default "fsl,ls2080a-pcie" if ARCH_LS2080A
262 default "fsl,ls1088a-pcie" if ARCH_LS1088A
263 default "fsl,lx2160a-pcie" if ARCH_LX2160A
265 This compatible is used to find pci controller node in Kernel DT
268 config HAS_FEATURE_GIC64K_ALIGN
270 default y if ARCH_LS1043A
272 config HAS_FEATURE_ENHANCED_MSI
274 default y if ARCH_LS1043A
276 menu "Layerscape PPA"
278 bool "FSL Layerscape PPA firmware support"
279 depends on !ARMV8_PSCI
280 select ARMV8_SEC_FIRMWARE_SUPPORT
281 select SEC_FIRMWARE_ARMV8_PSCI
282 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
284 The FSL Primary Protected Application (PPA) is a software component
285 which is loaded during boot stage, and then remains resident in RAM
286 and runs in the TrustZone after boot.
289 config SPL_FSL_LS_PPA
290 bool "FSL Layerscape PPA firmware support for SPL build"
291 depends on !ARMV8_PSCI
292 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
293 select SEC_FIRMWARE_ARMV8_PSCI
294 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
296 The FSL Primary Protected Application (PPA) is a software component
297 which is loaded during boot stage, and then remains resident in RAM
298 and runs in the TrustZone after boot. This is to load PPA during SPL
299 stage instead of the RAM version of U-Boot. Once PPA is initialized,
300 the rest of U-Boot (including RAM version) runs at EL2.
302 prompt "FSL Layerscape PPA firmware loading-media select"
303 depends on FSL_LS_PPA
304 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
305 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
306 default SYS_LS_PPA_FW_IN_XIP
308 config SYS_LS_PPA_FW_IN_XIP
311 Say Y here if the PPA firmware locate at XIP flash, such
312 as NOR or QSPI flash.
314 config SYS_LS_PPA_FW_IN_MMC
315 bool "eMMC or SD Card"
317 Say Y here if the PPA firmware locate at eMMC/SD card.
319 config SYS_LS_PPA_FW_IN_NAND
322 Say Y here if the PPA firmware locate at NAND flash.
326 config LS_PPA_ESBC_HDR_SIZE
327 hex "Length of PPA ESBC header"
328 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
331 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
332 NAND to memory to validate PPA image.
336 config SYS_FSL_ERRATUM_A008997
337 bool "Workaround for USB PHY erratum A008997"
339 config SYS_FSL_ERRATUM_A009007
342 Workaround for USB PHY erratum A009007
344 config SYS_FSL_ERRATUM_A009008
345 bool "Workaround for USB PHY erratum A009008"
347 config SYS_FSL_ERRATUM_A009798
348 bool "Workaround for USB PHY erratum A009798"
350 config SYS_FSL_ERRATUM_A010315
351 bool "Workaround for PCIe erratum A010315"
353 config SYS_FSL_ERRATUM_A010539
354 bool "Workaround for PIN MUX erratum A010539"
357 int "Maximum number of CPUs permitted for Layerscape"
358 default 2 if ARCH_LS1028A
359 default 4 if ARCH_LS1043A
360 default 4 if ARCH_LS1046A
361 default 16 if ARCH_LS2080A
362 default 8 if ARCH_LS1088A
363 default 16 if ARCH_LX2160A
366 Set this number to the maximum number of possible CPUs in the SoC.
367 SoCs may have multiple clusters with each cluster may have multiple
368 ports. If some ports are reserved but higher ports are used for
369 cores, count the reserved ports. This will allocate enough memory
370 in spin table to properly handle all cores.
373 bool "Fan controller"
375 Enable the EMC2305 fan controller for configuration of fan
381 Enable Freescale Secure Boot feature
384 bool "Init the QSPI AHB bus"
386 The default setting for QSPI AHB bus just support 3bytes addressing.
387 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
388 bus for those flashes to support the full QSPI flash size.
390 config SYS_CCI400_OFFSET
391 hex "Offset for CCI400 base"
392 depends on SYS_FSL_HAS_CCI400
393 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
394 default 0x180000 if FSL_LSCH2
396 Offset for CCI400 base
397 CCI400 base addr = CCSRBAR + CCI400_OFFSET
399 config SYS_FSL_IFC_BANK_COUNT
400 int "Maximum banks of Integrated flash controller"
401 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
402 default 4 if ARCH_LS1043A
403 default 4 if ARCH_LS1046A
404 default 8 if ARCH_LS2080A || ARCH_LS1088A
406 config SYS_FSL_HAS_CCI400
409 config SYS_FSL_HAS_CCN504
412 config SYS_FSL_HAS_CCN508
415 config SYS_FSL_HAS_DP_DDR
418 config SYS_FSL_SRDS_1
421 config SYS_FSL_SRDS_2
424 config SYS_NXP_SRDS_3
427 config SYS_HAS_SERDES
439 config FSL_TZPC_BP147
443 menu "Layerscape clock tree configuration"
444 depends on FSL_LSCH2 || FSL_LSCH3
447 bool "Enable clock tree initialization"
450 config CLUSTER_CLK_FREQ
451 int "Reference clock of core cluster"
452 depends on ARCH_LS1012A
455 This number is the reference clock frequency of core PLL.
456 For most platforms, the core PLL and Platform PLL have the same
457 reference clock, but for some platforms, LS1012A for instance,
458 they are provided sepatately.
460 config SYS_FSL_PCLK_DIV
461 int "Platform clock divider"
462 default 1 if ARCH_LS1028A
463 default 1 if ARCH_LS1043A
464 default 1 if ARCH_LS1046A
465 default 1 if ARCH_LS1088A
468 This is the divider that is used to derive Platform clock from
469 Platform PLL, in another word:
470 Platform_clk = Platform_PLL_freq / this_divider
472 config SYS_FSL_DSPI_CLK_DIV
473 int "DSPI clock divider"
474 default 1 if ARCH_LS1043A
477 This is the divider that is used to derive DSPI clock from Platform
478 clock, in another word DSPI_clk = Platform_clk / this_divider.
480 config SYS_FSL_DUART_CLK_DIV
481 int "DUART clock divider"
482 default 1 if ARCH_LS1043A
483 default 4 if ARCH_LX2160A
486 This is the divider that is used to derive DUART clock from Platform
487 clock, in another word DUART_clk = Platform_clk / this_divider.
489 config SYS_FSL_I2C_CLK_DIV
490 int "I2C clock divider"
491 default 1 if ARCH_LS1043A
492 default 4 if ARCH_LS1012A
493 default 4 if ARCH_LS1028A
494 default 8 if ARCH_LX2160A
495 default 8 if ARCH_LS1088A
498 This is the divider that is used to derive I2C clock from Platform
499 clock, in another word I2C_clk = Platform_clk / this_divider.
501 config SYS_FSL_IFC_CLK_DIV
502 int "IFC clock divider"
503 default 1 if ARCH_LS1043A
506 This is the divider that is used to derive IFC clock from Platform
507 clock, in another word IFC_clk = Platform_clk / this_divider.
509 config SYS_FSL_LPUART_CLK_DIV
510 int "LPUART clock divider"
511 default 1 if ARCH_LS1043A
514 This is the divider that is used to derive LPUART clock from Platform
515 clock, in another word LPUART_clk = Platform_clk / this_divider.
517 config SYS_FSL_SDHC_CLK_DIV
518 int "SDHC clock divider"
519 default 1 if ARCH_LS1043A
520 default 1 if ARCH_LS1012A
523 This is the divider that is used to derive SDHC clock from Platform
524 clock, in another word SDHC_clk = Platform_clk / this_divider.
526 config SYS_FSL_QMAN_CLK_DIV
527 int "QMAN clock divider"
528 default 1 if ARCH_LS1043A
531 This is the divider that is used to derive QMAN clock from Platform
532 clock, in another word QMAN_clk = Platform_clk / this_divider.
538 Reserve memory from the top, tracked by gd->arch.resv_ram. This
539 reserved RAM can be used by special driver that resides in memory
540 after U-Boot exits. It's up to implementation to allocate and allow
541 access to this reserved memory. For example, the reserved RAM can
542 be at the high end of physical memory. The reserve RAM may be
543 excluded from memory bank(s) passed to OS, or marked as reserved.
548 Ethernet controller 1, this is connected to
549 MAC17 for LX2160A or to MAC3 for other SoCs
550 Provides DPAA2 capabilities
555 Ethernet controller 2, this is connected to
556 MAC18 for LX2160A or to MAC4 for other SoCs
557 Provides DPAA2 capabilities
559 config SYS_FSL_ERRATUM_A008336
562 config SYS_FSL_ERRATUM_A008514
565 config SYS_FSL_ERRATUM_A008585
568 config SYS_FSL_ERRATUM_A008850
571 config SYS_FSL_ERRATUM_A009203
574 config SYS_FSL_ERRATUM_A009635
577 config SYS_FSL_ERRATUM_A009660
580 config SYS_FSL_ERRATUM_A009929
584 config SYS_FSL_HAS_RGMII
586 depends on SYS_FSL_EC1 || SYS_FSL_EC2
589 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
591 config HAS_FSL_XHCI_USB
593 default y if ARCH_LS1043A || ARCH_LS1046A
595 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
596 pins, select it when the pins are assigned to USB.