3 * David Feng <fenghua@phytium.com.cn>
6 * Alexander Graf <agraf@suse.de>
8 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/system.h>
13 #include <asm/armv8/mmu.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 #ifndef CONFIG_SYS_DCACHE_OFF
20 * With 4k page granule, a virtual address is split into 4 lookup parts
21 * spanning 9 bits each:
23 * _______________________________________________
25 * | 0 | Lv0 | Lv1 | Lv2 | Lv3 | off |
26 * |_______|_______|_______|_______|_______|_______|
27 * 63-48 47-39 38-30 29-21 20-12 11-00
31 * Lv0: FF8000000000 --
38 u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
45 /* Find the largest address we need to support */
46 for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
47 max_addr = max(max_addr, mem_map[i].base + mem_map[i].size);
49 /* Calculate the maximum physical (and thus virtual) address */
50 if (max_addr > (1ULL << 44)) {
53 } else if (max_addr > (1ULL << 42)) {
56 } else if (max_addr > (1ULL << 40)) {
59 } else if (max_addr > (1ULL << 36)) {
62 } else if (max_addr > (1ULL << 32)) {
71 tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
73 tcr = TCR_EL2_RSVD | (ips << 16);
75 tcr = TCR_EL3_RSVD | (ips << 16);
78 /* PTWs cacheable, inner/outer WBWA and inner shareable */
79 tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
80 tcr |= TCR_T0SZ(va_bits);
90 #define MAX_PTE_ENTRIES 512
92 static int pte_type(u64 *pte)
94 return *pte & PTE_TYPE_MASK;
97 /* Returns the LSB number for a PTE on level <level> */
98 static int level2shift(int level)
100 /* Page is 12 bits wide, every level translates 9 bits */
101 return (12 + 9 * (3 - level));
104 static u64 *find_pte(u64 addr, int level)
112 debug("addr=%llx level=%d\n", addr, level);
114 get_tcr(0, NULL, &va_bits);
118 if (level < start_level)
121 /* Walk through all page table levels to find our PTE */
122 pte = (u64*)gd->arch.tlb_addr;
123 for (i = start_level; i < 4; i++) {
124 idx = (addr >> level2shift(i)) & 0x1FF;
126 debug("idx=%llx PTE %p at level %d: %llx\n", idx, pte, i, *pte);
131 /* PTE is no table (either invalid or block), can't traverse */
132 if (pte_type(pte) != PTE_TYPE_TABLE)
134 /* Off to the next level */
135 pte = (u64*)(*pte & 0x0000fffffffff000ULL);
138 /* Should never reach here */
142 /* Returns and creates a new full table (512 entries) */
143 static u64 *create_table(void)
145 u64 *new_table = (u64*)gd->arch.tlb_fillptr;
146 u64 pt_len = MAX_PTE_ENTRIES * sizeof(u64);
148 /* Allocate MAX_PTE_ENTRIES pte entries */
149 gd->arch.tlb_fillptr += pt_len;
151 if (gd->arch.tlb_fillptr - gd->arch.tlb_addr > gd->arch.tlb_size)
152 panic("Insufficient RAM for page table: 0x%lx > 0x%lx. "
153 "Please increase the size in get_page_table_size()",
154 gd->arch.tlb_fillptr - gd->arch.tlb_addr,
157 /* Mark all entries as invalid */
158 memset(new_table, 0, pt_len);
163 static void set_pte_table(u64 *pte, u64 *table)
165 /* Point *pte to the new table */
166 debug("Setting %p to addr=%p\n", pte, table);
167 *pte = PTE_TYPE_TABLE | (ulong)table;
170 /* Splits a block PTE into table with subpages spanning the old block */
171 static void split_block(u64 *pte, int level)
176 /* level describes the parent level, we need the child ones */
177 int levelshift = level2shift(level + 1);
179 if (pte_type(pte) != PTE_TYPE_BLOCK)
180 panic("PTE %p (%llx) is not a block. Some driver code wants to "
181 "modify dcache settings for an range not covered in "
182 "mem_map.", pte, old_pte);
184 new_table = create_table();
185 debug("Splitting pte %p (%llx) into %p\n", pte, old_pte, new_table);
187 for (i = 0; i < MAX_PTE_ENTRIES; i++) {
188 new_table[i] = old_pte | (i << levelshift);
190 /* Level 3 block PTEs have the table type */
191 if ((level + 1) == 3)
192 new_table[i] |= PTE_TYPE_TABLE;
194 debug("Setting new_table[%lld] = %llx\n", i, new_table[i]);
197 /* Set the new table into effect */
198 set_pte_table(pte, new_table);
201 /* Add one mm_region map entry to the page tables */
202 static void add_map(struct mm_region *map)
205 u64 addr = map->base;
206 u64 size = map->size;
207 u64 attrs = map->attrs | PTE_TYPE_BLOCK | PTE_BLOCK_AF;
213 pte = find_pte(addr, 0);
214 if (pte && (pte_type(pte) == PTE_TYPE_FAULT)) {
215 debug("Creating table for addr 0x%llx\n", addr);
216 new_table = create_table();
217 set_pte_table(pte, new_table);
220 for (level = 1; level < 4; level++) {
221 pte = find_pte(addr, level);
223 panic("pte not found\n");
224 blocksize = 1ULL << level2shift(level);
225 debug("Checking if pte fits for addr=%llx size=%llx "
226 "blocksize=%llx\n", addr, size, blocksize);
227 if (size >= blocksize && !(addr & (blocksize - 1))) {
228 /* Page fits, create block PTE */
229 debug("Setting PTE %p to block addr=%llx\n",
235 } else if (pte_type(pte) == PTE_TYPE_FAULT) {
236 /* Page doesn't fit, create subpages */
237 debug("Creating subtable for addr 0x%llx "
238 "blksize=%llx\n", addr, blocksize);
239 new_table = create_table();
240 set_pte_table(pte, new_table);
241 } else if (pte_type(pte) == PTE_TYPE_BLOCK) {
242 debug("Split block into subtable for addr 0x%llx blksize=0x%llx\n",
244 split_block(pte, level);
257 * This is a recursively called function to count the number of
258 * page tables we need to cover a particular PTE range. If you
259 * call this with level = -1 you basically get the full 48 bit
262 static int count_required_pts(u64 addr, int level, u64 maxaddr)
264 int levelshift = level2shift(level);
265 u64 levelsize = 1ULL << levelshift;
266 u64 levelmask = levelsize - 1;
267 u64 levelend = addr + levelsize;
270 enum pte_type pte_type = PTE_INVAL;
272 for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) {
273 struct mm_region *map = &mem_map[i];
274 u64 start = map->base;
275 u64 end = start + map->size;
277 /* Check if the PTE would overlap with the map */
278 if (max(addr, start) <= min(levelend, end)) {
279 start = max(addr, start);
280 end = min(levelend, end);
282 /* We need a sub-pt for this level */
283 if ((start & levelmask) || (end & levelmask)) {
284 pte_type = PTE_LEVEL;
288 /* Lv0 can not do block PTEs, so do levels here too */
290 pte_type = PTE_LEVEL;
294 /* PTE is active, but fits into a block */
295 pte_type = PTE_BLOCK;
300 * Block PTEs at this level are already covered by the parent page
301 * table, so we only need to count sub page tables.
303 if (pte_type == PTE_LEVEL) {
304 int sublevel = level + 1;
305 u64 sublevelsize = 1ULL << level2shift(sublevel);
307 /* Account for the new sub page table ... */
310 /* ... and for all child page tables that one might have */
311 for (i = 0; i < MAX_PTE_ENTRIES; i++) {
312 r += count_required_pts(addr, sublevel, maxaddr);
313 addr += sublevelsize;
315 if (addr >= maxaddr) {
317 * We reached the end of address space, no need
318 * to look any further.
328 /* Returns the estimated required size of all page tables */
329 __weak u64 get_page_table_size(void)
331 u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
336 get_tcr(0, NULL, &va_bits);
340 /* Account for all page tables we would need to cover our memory map */
341 size = one_pt * count_required_pts(0, start_level - 1, 1ULL << va_bits);
344 * We need to duplicate our page table once to have an emergency pt to
345 * resort to when splitting page tables later on
350 * We may need to split page tables later on if dcache settings change,
351 * so reserve up to 4 (random pick) page tables for that.
358 void setup_pgtables(void)
362 if (!gd->arch.tlb_fillptr || !gd->arch.tlb_addr)
363 panic("Page table pointer not setup.");
366 * Allocate the first level we're on with invalidate entries.
367 * If the starting level is 0 (va_bits >= 39), then this is our
368 * Lv0 page table, otherwise it's the entry Lv1 page table.
372 /* Now add all MMU table entries one after another to the table */
373 for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
374 add_map(&mem_map[i]);
377 static void setup_all_pgtables(void)
379 u64 tlb_addr = gd->arch.tlb_addr;
381 /* Reset the fill ptr */
382 gd->arch.tlb_fillptr = tlb_addr;
384 /* Create normal system page tables */
387 /* Create emergency page tables */
388 gd->arch.tlb_addr = gd->arch.tlb_fillptr;
390 gd->arch.tlb_emerg = gd->arch.tlb_addr;
391 gd->arch.tlb_addr = tlb_addr;
394 /* to activate the MMU we need to set up virtual memory */
395 __weak void mmu_setup(void)
399 /* Set up page tables only once */
400 if (!gd->arch.tlb_fillptr)
401 setup_all_pgtables();
404 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
408 set_sctlr(get_sctlr() | CR_M);
412 * Performs a invalidation of the entire data cache at all levels
414 void invalidate_dcache_all(void)
416 __asm_invalidate_dcache_all();
420 * Performs a clean & invalidation of the entire data cache at all levels.
421 * This function needs to be inline to avoid using stack.
422 * __asm_flush_l3_cache return status of timeout
424 inline void flush_dcache_all(void)
428 __asm_flush_dcache_all();
429 ret = __asm_flush_l3_cache();
431 debug("flushing dcache returns 0x%x\n", ret);
433 debug("flushing dcache successfully.\n");
437 * Invalidates range in all levels of D-cache/unified cache
439 void invalidate_dcache_range(unsigned long start, unsigned long stop)
441 __asm_flush_dcache_range(start, stop);
445 * Flush range(clean & invalidate) from all levels of D-cache/unified cache
447 void flush_dcache_range(unsigned long start, unsigned long stop)
449 __asm_flush_dcache_range(start, stop);
452 void dcache_enable(void)
454 /* The data cache is not active unless the mmu is enabled */
455 if (!(get_sctlr() & CR_M)) {
456 invalidate_dcache_all();
457 __asm_invalidate_tlb_all();
461 set_sctlr(get_sctlr() | CR_C);
464 void dcache_disable(void)
470 /* if cache isn't enabled no need to disable */
474 set_sctlr(sctlr & ~(CR_C|CR_M));
477 __asm_invalidate_tlb_all();
480 int dcache_status(void)
482 return (get_sctlr() & CR_C) != 0;
485 u64 *__weak arch_get_page_table(void) {
486 puts("No page table offset defined\n");
491 static bool is_aligned(u64 addr, u64 size, u64 align)
493 return !(addr & (align - 1)) && !(size & (align - 1));
496 static u64 set_one_region(u64 start, u64 size, u64 attrs, int level)
498 int levelshift = level2shift(level);
499 u64 levelsize = 1ULL << levelshift;
500 u64 *pte = find_pte(start, level);
502 /* Can we can just modify the current level block PTE? */
503 if (is_aligned(start, size, levelsize)) {
504 *pte &= ~PMD_ATTRINDX_MASK;
506 debug("Set attrs=%llx pte=%p level=%d\n", attrs, pte, level);
511 /* Unaligned or doesn't fit, maybe split block into table */
512 debug("addr=%llx level=%d pte=%p (%llx)\n", start, level, pte, *pte);
514 /* Maybe we need to split the block into a table */
515 if (pte_type(pte) == PTE_TYPE_BLOCK)
516 split_block(pte, level);
518 /* And then double-check it became a table or already is one */
519 if (pte_type(pte) != PTE_TYPE_TABLE)
520 panic("PTE %p (%llx) for addr=%llx should be a table",
523 /* Roll on to the next page table level */
527 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
528 enum dcache_option option)
530 u64 attrs = PMD_ATTRINDX(option);
531 u64 real_start = start;
532 u64 real_size = size;
534 debug("start=%lx size=%lx\n", (ulong)start, (ulong)size);
536 if (!gd->arch.tlb_emerg)
537 panic("Emergency page table not setup.");
540 * We can not modify page tables that we're currently running on,
541 * so we first need to switch to the "emergency" page tables where
542 * we can safely modify our primary page tables and then switch back
544 __asm_switch_ttbr(gd->arch.tlb_emerg);
547 * Loop through the address range until we find a page granule that fits
548 * our alignment constraints, then set it to the new cache attributes
554 for (level = 1; level < 4; level++) {
555 r = set_one_region(start, size, attrs, level);
557 /* PTE successfully replaced */
566 /* We're done modifying page tables, switch back to our primary ones */
567 __asm_switch_ttbr(gd->arch.tlb_addr);
570 * Make sure there's nothing stale in dcache for a region that might
571 * have caches off now
573 flush_dcache_range(real_start, real_start + real_size);
576 #else /* CONFIG_SYS_DCACHE_OFF */
579 * For SPL builds, we may want to not have dcache enabled. Any real U-Boot
580 * running however really wants to have dcache and the MMU active. Check that
581 * everything is sane and give the developer a hint if it isn't.
583 #ifndef CONFIG_SPL_BUILD
584 #error Please describe your MMU layout in CONFIG_SYS_MEM_MAP and enable dcache.
587 void invalidate_dcache_all(void)
591 void flush_dcache_all(void)
595 void dcache_enable(void)
599 void dcache_disable(void)
603 int dcache_status(void)
608 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
609 enum dcache_option option)
613 #endif /* CONFIG_SYS_DCACHE_OFF */
615 #ifndef CONFIG_SYS_ICACHE_OFF
617 void icache_enable(void)
619 __asm_invalidate_icache_all();
620 set_sctlr(get_sctlr() | CR_I);
623 void icache_disable(void)
625 set_sctlr(get_sctlr() & ~CR_I);
628 int icache_status(void)
630 return (get_sctlr() & CR_I) != 0;
633 void invalidate_icache_all(void)
635 __asm_invalidate_icache_all();
638 #else /* CONFIG_SYS_ICACHE_OFF */
640 void icache_enable(void)
644 void icache_disable(void)
648 int icache_status(void)
653 void invalidate_icache_all(void)
657 #endif /* CONFIG_SYS_ICACHE_OFF */
660 * Enable dCache & iCache, whether cache is actually enabled
661 * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
663 void __weak enable_caches(void)