3 * David Feng <fenghua@phytium.com.cn>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/system.h>
10 #include <asm/armv8/mmu.h>
12 DECLARE_GLOBAL_DATA_PTR;
14 #ifndef CONFIG_SYS_DCACHE_OFF
15 void set_pgtable_section(u64 *page_table, u64 index, u64 section,
20 value = section | PMD_TYPE_SECT | PMD_SECT_AF;
21 value |= PMD_ATTRINDX(memory_type);
22 page_table[index] = value;
25 /* to activate the MMU we need to set up virtual memory */
26 static void mmu_setup(void)
30 u64 *page_table = (u64 *)gd->arch.tlb_addr;
32 /* Setup an identity-mapping for all spaces */
33 for (i = 0; i < (PGTABLE_SIZE >> 3); i++) {
34 set_pgtable_section(page_table, i, i << SECTION_SHIFT,
38 /* Setup an identity-mapping for all RAM space */
39 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
40 ulong start = bd->bi_dram[i].start;
41 ulong end = bd->bi_dram[i].start + bd->bi_dram[i].size;
42 for (j = start >> SECTION_SHIFT;
43 j < end >> SECTION_SHIFT; j++) {
44 set_pgtable_section(page_table, j, j << SECTION_SHIFT,
52 set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
53 TCR_FLAGS | TCR_EL1_IPS_BITS,
56 set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
57 TCR_FLAGS | TCR_EL2_IPS_BITS,
60 set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
61 TCR_FLAGS | TCR_EL3_IPS_BITS,
65 set_sctlr(get_sctlr() | CR_M);
69 * Performs a invalidation of the entire data cache at all levels
71 void invalidate_dcache_all(void)
73 __asm_invalidate_dcache_all();
76 void __weak flush_l3_cache(void)
81 * Performs a clean & invalidation of the entire data cache at all levels
83 void flush_dcache_all(void)
85 __asm_flush_dcache_all();
90 * Invalidates range in all levels of D-cache/unified cache
92 void invalidate_dcache_range(unsigned long start, unsigned long stop)
94 __asm_flush_dcache_range(start, stop);
98 * Flush range(clean & invalidate) from all levels of D-cache/unified cache
100 void flush_dcache_range(unsigned long start, unsigned long stop)
102 __asm_flush_dcache_range(start, stop);
105 void dcache_enable(void)
107 /* The data cache is not active unless the mmu is enabled */
108 if (!(get_sctlr() & CR_M)) {
109 invalidate_dcache_all();
110 __asm_invalidate_tlb_all();
114 set_sctlr(get_sctlr() | CR_C);
117 void dcache_disable(void)
123 /* if cache isn't enabled no need to disable */
127 set_sctlr(sctlr & ~(CR_C|CR_M));
130 __asm_invalidate_tlb_all();
133 int dcache_status(void)
135 return (get_sctlr() & CR_C) != 0;
138 #else /* CONFIG_SYS_DCACHE_OFF */
140 void invalidate_dcache_all(void)
144 void flush_dcache_all(void)
148 void invalidate_dcache_range(unsigned long start, unsigned long stop)
152 void flush_dcache_range(unsigned long start, unsigned long stop)
156 void dcache_enable(void)
160 void dcache_disable(void)
164 int dcache_status(void)
169 #endif /* CONFIG_SYS_DCACHE_OFF */
171 #ifndef CONFIG_SYS_ICACHE_OFF
173 void icache_enable(void)
175 __asm_invalidate_icache_all();
176 set_sctlr(get_sctlr() | CR_I);
179 void icache_disable(void)
181 set_sctlr(get_sctlr() & ~CR_I);
184 int icache_status(void)
186 return (get_sctlr() & CR_I) != 0;
189 void invalidate_icache_all(void)
191 __asm_invalidate_icache_all();
194 #else /* CONFIG_SYS_ICACHE_OFF */
196 void icache_enable(void)
200 void icache_disable(void)
204 int icache_status(void)
209 void invalidate_icache_all(void)
213 #endif /* CONFIG_SYS_ICACHE_OFF */
216 * Enable dCache & iCache, whether cache is actually enabled
217 * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
219 void __weak enable_caches(void)
226 * Flush range from all levels of d-cache/unified-cache
228 void flush_cache(unsigned long start, unsigned long size)
230 flush_dcache_range(start, start + size);