1 // SPDX-License-Identifier: GPL-2.0+
4 * David Feng <fenghua@phytium.com.cn>
7 * Alexander Graf <agraf@suse.de>
11 #include <asm/system.h>
12 #include <asm/armv8/mmu.h>
14 DECLARE_GLOBAL_DATA_PTR;
16 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
19 * With 4k page granule, a virtual address is split into 4 lookup parts
20 * spanning 9 bits each:
22 * _______________________________________________
24 * | 0 | Lv0 | Lv1 | Lv2 | Lv3 | off |
25 * |_______|_______|_______|_______|_______|_______|
26 * 63-48 47-39 38-30 29-21 20-12 11-00
30 * Lv0: FF8000000000 --
37 u64 get_tcr(int el, u64 *pips, u64 *pva_bits)
44 /* Find the largest address we need to support */
45 for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
46 max_addr = max(max_addr, mem_map[i].virt + mem_map[i].size);
48 /* Calculate the maximum physical (and thus virtual) address */
49 if (max_addr > (1ULL << 44)) {
52 } else if (max_addr > (1ULL << 42)) {
55 } else if (max_addr > (1ULL << 40)) {
58 } else if (max_addr > (1ULL << 36)) {
61 } else if (max_addr > (1ULL << 32)) {
70 tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
72 tcr = TCR_EL2_RSVD | (ips << 16);
74 tcr = TCR_EL3_RSVD | (ips << 16);
77 /* PTWs cacheable, inner/outer WBWA and inner shareable */
78 tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA;
79 tcr |= TCR_T0SZ(va_bits);
89 #define MAX_PTE_ENTRIES 512
91 static int pte_type(u64 *pte)
93 return *pte & PTE_TYPE_MASK;
96 /* Returns the LSB number for a PTE on level <level> */
97 static int level2shift(int level)
99 /* Page is 12 bits wide, every level translates 9 bits */
100 return (12 + 9 * (3 - level));
103 static u64 *find_pte(u64 addr, int level)
111 debug("addr=%llx level=%d\n", addr, level);
113 get_tcr(0, NULL, &va_bits);
117 if (level < start_level)
120 /* Walk through all page table levels to find our PTE */
121 pte = (u64*)gd->arch.tlb_addr;
122 for (i = start_level; i < 4; i++) {
123 idx = (addr >> level2shift(i)) & 0x1FF;
125 debug("idx=%llx PTE %p at level %d: %llx\n", idx, pte, i, *pte);
130 /* PTE is no table (either invalid or block), can't traverse */
131 if (pte_type(pte) != PTE_TYPE_TABLE)
133 /* Off to the next level */
134 pte = (u64*)(*pte & 0x0000fffffffff000ULL);
137 /* Should never reach here */
141 /* Returns and creates a new full table (512 entries) */
142 static u64 *create_table(void)
144 u64 *new_table = (u64*)gd->arch.tlb_fillptr;
145 u64 pt_len = MAX_PTE_ENTRIES * sizeof(u64);
147 /* Allocate MAX_PTE_ENTRIES pte entries */
148 gd->arch.tlb_fillptr += pt_len;
150 if (gd->arch.tlb_fillptr - gd->arch.tlb_addr > gd->arch.tlb_size)
151 panic("Insufficient RAM for page table: 0x%lx > 0x%lx. "
152 "Please increase the size in get_page_table_size()",
153 gd->arch.tlb_fillptr - gd->arch.tlb_addr,
156 /* Mark all entries as invalid */
157 memset(new_table, 0, pt_len);
162 static void set_pte_table(u64 *pte, u64 *table)
164 /* Point *pte to the new table */
165 debug("Setting %p to addr=%p\n", pte, table);
166 *pte = PTE_TYPE_TABLE | (ulong)table;
169 /* Splits a block PTE into table with subpages spanning the old block */
170 static void split_block(u64 *pte, int level)
175 /* level describes the parent level, we need the child ones */
176 int levelshift = level2shift(level + 1);
178 if (pte_type(pte) != PTE_TYPE_BLOCK)
179 panic("PTE %p (%llx) is not a block. Some driver code wants to "
180 "modify dcache settings for an range not covered in "
181 "mem_map.", pte, old_pte);
183 new_table = create_table();
184 debug("Splitting pte %p (%llx) into %p\n", pte, old_pte, new_table);
186 for (i = 0; i < MAX_PTE_ENTRIES; i++) {
187 new_table[i] = old_pte | (i << levelshift);
189 /* Level 3 block PTEs have the table type */
190 if ((level + 1) == 3)
191 new_table[i] |= PTE_TYPE_TABLE;
193 debug("Setting new_table[%lld] = %llx\n", i, new_table[i]);
196 /* Set the new table into effect */
197 set_pte_table(pte, new_table);
200 /* Add one mm_region map entry to the page tables */
201 static void add_map(struct mm_region *map)
204 u64 virt = map->virt;
205 u64 phys = map->phys;
206 u64 size = map->size;
207 u64 attrs = map->attrs | PTE_TYPE_BLOCK | PTE_BLOCK_AF;
213 pte = find_pte(virt, 0);
214 if (pte && (pte_type(pte) == PTE_TYPE_FAULT)) {
215 debug("Creating table for virt 0x%llx\n", virt);
216 new_table = create_table();
217 set_pte_table(pte, new_table);
220 for (level = 1; level < 4; level++) {
221 pte = find_pte(virt, level);
223 panic("pte not found\n");
225 blocksize = 1ULL << level2shift(level);
226 debug("Checking if pte fits for virt=%llx size=%llx blocksize=%llx\n",
227 virt, size, blocksize);
228 if (size >= blocksize && !(virt & (blocksize - 1))) {
229 /* Page fits, create block PTE */
230 debug("Setting PTE %p to block virt=%llx\n",
233 *pte = phys | attrs | PTE_TYPE_PAGE;
240 } else if (pte_type(pte) == PTE_TYPE_FAULT) {
241 /* Page doesn't fit, create subpages */
242 debug("Creating subtable for virt 0x%llx blksize=%llx\n",
244 new_table = create_table();
245 set_pte_table(pte, new_table);
246 } else if (pte_type(pte) == PTE_TYPE_BLOCK) {
247 debug("Split block into subtable for virt 0x%llx blksize=0x%llx\n",
249 split_block(pte, level);
262 * This is a recursively called function to count the number of
263 * page tables we need to cover a particular PTE range. If you
264 * call this with level = -1 you basically get the full 48 bit
267 static int count_required_pts(u64 addr, int level, u64 maxaddr)
269 int levelshift = level2shift(level);
270 u64 levelsize = 1ULL << levelshift;
271 u64 levelmask = levelsize - 1;
272 u64 levelend = addr + levelsize;
275 enum pte_type pte_type = PTE_INVAL;
277 for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) {
278 struct mm_region *map = &mem_map[i];
279 u64 start = map->virt;
280 u64 end = start + map->size;
282 /* Check if the PTE would overlap with the map */
283 if (max(addr, start) <= min(levelend, end)) {
284 start = max(addr, start);
285 end = min(levelend, end);
287 /* We need a sub-pt for this level */
288 if ((start & levelmask) || (end & levelmask)) {
289 pte_type = PTE_LEVEL;
293 /* Lv0 can not do block PTEs, so do levels here too */
295 pte_type = PTE_LEVEL;
299 /* PTE is active, but fits into a block */
300 pte_type = PTE_BLOCK;
305 * Block PTEs at this level are already covered by the parent page
306 * table, so we only need to count sub page tables.
308 if (pte_type == PTE_LEVEL) {
309 int sublevel = level + 1;
310 u64 sublevelsize = 1ULL << level2shift(sublevel);
312 /* Account for the new sub page table ... */
315 /* ... and for all child page tables that one might have */
316 for (i = 0; i < MAX_PTE_ENTRIES; i++) {
317 r += count_required_pts(addr, sublevel, maxaddr);
318 addr += sublevelsize;
320 if (addr >= maxaddr) {
322 * We reached the end of address space, no need
323 * to look any further.
333 /* Returns the estimated required size of all page tables */
334 __weak u64 get_page_table_size(void)
336 u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
341 get_tcr(0, NULL, &va_bits);
345 /* Account for all page tables we would need to cover our memory map */
346 size = one_pt * count_required_pts(0, start_level - 1, 1ULL << va_bits);
349 * We need to duplicate our page table once to have an emergency pt to
350 * resort to when splitting page tables later on
355 * We may need to split page tables later on if dcache settings change,
356 * so reserve up to 4 (random pick) page tables for that.
363 void setup_pgtables(void)
367 if (!gd->arch.tlb_fillptr || !gd->arch.tlb_addr)
368 panic("Page table pointer not setup.");
371 * Allocate the first level we're on with invalidate entries.
372 * If the starting level is 0 (va_bits >= 39), then this is our
373 * Lv0 page table, otherwise it's the entry Lv1 page table.
377 /* Now add all MMU table entries one after another to the table */
378 for (i = 0; mem_map[i].size || mem_map[i].attrs; i++)
379 add_map(&mem_map[i]);
382 static void setup_all_pgtables(void)
384 u64 tlb_addr = gd->arch.tlb_addr;
385 u64 tlb_size = gd->arch.tlb_size;
387 /* Reset the fill ptr */
388 gd->arch.tlb_fillptr = tlb_addr;
390 /* Create normal system page tables */
393 /* Create emergency page tables */
394 gd->arch.tlb_size -= (uintptr_t)gd->arch.tlb_fillptr -
395 (uintptr_t)gd->arch.tlb_addr;
396 gd->arch.tlb_addr = gd->arch.tlb_fillptr;
398 gd->arch.tlb_emerg = gd->arch.tlb_addr;
399 gd->arch.tlb_addr = tlb_addr;
400 gd->arch.tlb_size = tlb_size;
403 /* to activate the MMU we need to set up virtual memory */
404 __weak void mmu_setup(void)
408 /* Set up page tables only once */
409 if (!gd->arch.tlb_fillptr)
410 setup_all_pgtables();
413 set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
417 set_sctlr(get_sctlr() | CR_M);
421 * Performs a invalidation of the entire data cache at all levels
423 void invalidate_dcache_all(void)
425 __asm_invalidate_dcache_all();
426 __asm_invalidate_l3_dcache();
430 * Performs a clean & invalidation of the entire data cache at all levels.
431 * This function needs to be inline to avoid using stack.
432 * __asm_flush_l3_dcache return status of timeout
434 inline void flush_dcache_all(void)
438 __asm_flush_dcache_all();
439 ret = __asm_flush_l3_dcache();
441 debug("flushing dcache returns 0x%x\n", ret);
443 debug("flushing dcache successfully.\n");
446 #ifndef CONFIG_SYS_DISABLE_DCACHE_OPS
448 * Invalidates range in all levels of D-cache/unified cache
450 void invalidate_dcache_range(unsigned long start, unsigned long stop)
452 __asm_invalidate_dcache_range(start, stop);
456 * Flush range(clean & invalidate) from all levels of D-cache/unified cache
458 void flush_dcache_range(unsigned long start, unsigned long stop)
460 __asm_flush_dcache_range(start, stop);
463 void invalidate_dcache_range(unsigned long start, unsigned long stop)
467 void flush_dcache_range(unsigned long start, unsigned long stop)
470 #endif /* CONFIG_SYS_DISABLE_DCACHE_OPS */
472 void dcache_enable(void)
474 /* The data cache is not active unless the mmu is enabled */
475 if (!(get_sctlr() & CR_M)) {
476 invalidate_dcache_all();
477 __asm_invalidate_tlb_all();
481 set_sctlr(get_sctlr() | CR_C);
484 void dcache_disable(void)
490 /* if cache isn't enabled no need to disable */
494 set_sctlr(sctlr & ~(CR_C|CR_M));
497 __asm_invalidate_tlb_all();
500 int dcache_status(void)
502 return (get_sctlr() & CR_C) != 0;
505 u64 *__weak arch_get_page_table(void) {
506 puts("No page table offset defined\n");
511 static bool is_aligned(u64 addr, u64 size, u64 align)
513 return !(addr & (align - 1)) && !(size & (align - 1));
516 /* Use flag to indicate if attrs has more than d-cache attributes */
517 static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level)
519 int levelshift = level2shift(level);
520 u64 levelsize = 1ULL << levelshift;
521 u64 *pte = find_pte(start, level);
523 /* Can we can just modify the current level block PTE? */
524 if (is_aligned(start, size, levelsize)) {
526 *pte &= ~PMD_ATTRMASK;
527 *pte |= attrs & PMD_ATTRMASK;
529 *pte &= ~PMD_ATTRINDX_MASK;
530 *pte |= attrs & PMD_ATTRINDX_MASK;
532 debug("Set attrs=%llx pte=%p level=%d\n", attrs, pte, level);
537 /* Unaligned or doesn't fit, maybe split block into table */
538 debug("addr=%llx level=%d pte=%p (%llx)\n", start, level, pte, *pte);
540 /* Maybe we need to split the block into a table */
541 if (pte_type(pte) == PTE_TYPE_BLOCK)
542 split_block(pte, level);
544 /* And then double-check it became a table or already is one */
545 if (pte_type(pte) != PTE_TYPE_TABLE)
546 panic("PTE %p (%llx) for addr=%llx should be a table",
549 /* Roll on to the next page table level */
553 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
554 enum dcache_option option)
556 u64 attrs = PMD_ATTRINDX(option);
557 u64 real_start = start;
558 u64 real_size = size;
560 debug("start=%lx size=%lx\n", (ulong)start, (ulong)size);
562 if (!gd->arch.tlb_emerg)
563 panic("Emergency page table not setup.");
566 * We can not modify page tables that we're currently running on,
567 * so we first need to switch to the "emergency" page tables where
568 * we can safely modify our primary page tables and then switch back
570 __asm_switch_ttbr(gd->arch.tlb_emerg);
573 * Loop through the address range until we find a page granule that fits
574 * our alignment constraints, then set it to the new cache attributes
580 for (level = 1; level < 4; level++) {
581 /* Set d-cache attributes only */
582 r = set_one_region(start, size, attrs, false, level);
584 /* PTE successfully replaced */
593 /* We're done modifying page tables, switch back to our primary ones */
594 __asm_switch_ttbr(gd->arch.tlb_addr);
597 * Make sure there's nothing stale in dcache for a region that might
598 * have caches off now
600 flush_dcache_range(real_start, real_start + real_size);
604 * Modify MMU table for a region with updated PXN/UXN/Memory type/valid bits.
605 * The procecess is break-before-make. The target region will be marked as
606 * invalid during the process of changing.
608 void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs)
616 * Loop through the address range until we find a page granule that fits
617 * our alignment constraints, then set it to "invalid".
620 for (level = 1; level < 4; level++) {
621 /* Set PTE to fault */
622 r = set_one_region(start, size, PTE_TYPE_FAULT, true,
625 /* PTE successfully invalidated */
633 flush_dcache_range(gd->arch.tlb_addr,
634 gd->arch.tlb_addr + gd->arch.tlb_size);
635 __asm_invalidate_tlb_all();
638 * Loop through the address range until we find a page granule that fits
639 * our alignment constraints, then set it to the new cache attributes
644 for (level = 1; level < 4; level++) {
645 /* Set PTE to new attributes */
646 r = set_one_region(start, size, attrs, true, level);
648 /* PTE successfully updated */
655 flush_dcache_range(gd->arch.tlb_addr,
656 gd->arch.tlb_addr + gd->arch.tlb_size);
657 __asm_invalidate_tlb_all();
660 #else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
663 * For SPL builds, we may want to not have dcache enabled. Any real U-Boot
664 * running however really wants to have dcache and the MMU active. Check that
665 * everything is sane and give the developer a hint if it isn't.
667 #ifndef CONFIG_SPL_BUILD
668 #error Please describe your MMU layout in CONFIG_SYS_MEM_MAP and enable dcache.
671 void invalidate_dcache_all(void)
675 void flush_dcache_all(void)
679 void dcache_enable(void)
683 void dcache_disable(void)
687 int dcache_status(void)
692 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
693 enum dcache_option option)
697 #endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
699 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
701 void icache_enable(void)
703 invalidate_icache_all();
704 set_sctlr(get_sctlr() | CR_I);
707 void icache_disable(void)
709 set_sctlr(get_sctlr() & ~CR_I);
712 int icache_status(void)
714 return (get_sctlr() & CR_I) != 0;
717 void invalidate_icache_all(void)
719 __asm_invalidate_icache_all();
720 __asm_invalidate_l3_icache();
723 #else /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
725 void icache_enable(void)
729 void icache_disable(void)
733 int icache_status(void)
738 void invalidate_icache_all(void)
742 #endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
745 * Enable dCache & iCache, whether cache is actually enabled
746 * depend on CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF
748 void __weak enable_caches(void)