3 * Vikas Manocha, ST Micoelectronics, vikas.manocha@st.com.
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/armv7m.h>
13 /* Cache maintenance operation registers */
15 #define V7M_CACHE_REG_ICIALLU ((u32 *)(V7M_CACHE_MAINT_BASE + 0x00))
16 #define INVAL_ICACHE_POU 0
17 #define V7M_CACHE_REG_ICIMVALU ((u32 *)(V7M_CACHE_MAINT_BASE + 0x08))
18 #define V7M_CACHE_REG_DCIMVAC ((u32 *)(V7M_CACHE_MAINT_BASE + 0x0C))
19 #define V7M_CACHE_REG_DCISW ((u32 *)(V7M_CACHE_MAINT_BASE + 0x10))
20 #define V7M_CACHE_REG_DCCMVAU ((u32 *)(V7M_CACHE_MAINT_BASE + 0x14))
21 #define V7M_CACHE_REG_DCCMVAC ((u32 *)(V7M_CACHE_MAINT_BASE + 0x18))
22 #define V7M_CACHE_REG_DCCSW ((u32 *)(V7M_CACHE_MAINT_BASE + 0x1C))
23 #define V7M_CACHE_REG_DCCIMVAC ((u32 *)(V7M_CACHE_MAINT_BASE + 0x20))
24 #define V7M_CACHE_REG_DCCISW ((u32 *)(V7M_CACHE_MAINT_BASE + 0x24))
28 /* armv7m processor feature registers */
30 #define V7M_PROC_REG_CLIDR ((u32 *)(V7M_PROC_FTR_BASE + 0x00))
31 #define V7M_PROC_REG_CTR ((u32 *)(V7M_PROC_FTR_BASE + 0x04))
32 #define V7M_PROC_REG_CCSIDR ((u32 *)(V7M_PROC_FTR_BASE + 0x08))
33 #define MASK_NUM_WAYS GENMASK(12, 3)
34 #define MASK_NUM_SETS GENMASK(27, 13)
35 #define CLINE_SIZE_MASK GENMASK(2, 0)
36 #define NUM_WAYS_SHIFT 3
37 #define NUM_SETS_SHIFT 13
38 #define V7M_PROC_REG_CSSELR ((u32 *)(V7M_PROC_FTR_BASE + 0x0C))
39 #define SEL_I_OR_D BIT(0)
46 /* PoU : Point of Unification, Poc: Point of Coherency */
48 INVALIDATE_POU, /* i-cache invalidate by address */
49 INVALIDATE_POC, /* d-cache invalidate by address */
50 INVALIDATE_SET_WAY, /* d-cache invalidate by sets/ways */
51 FLUSH_POU, /* d-cache clean by address to the PoU */
52 FLUSH_POC, /* d-cache clean by address to the PoC */
53 FLUSH_SET_WAY, /* d-cache clean by sets/ways */
54 FLUSH_INVAL_POC, /* d-cache clean & invalidate by addr to PoC */
55 FLUSH_INVAL_SET_WAY, /* d-cache clean & invalidate by set/ways */
58 #ifndef CONFIG_SYS_DCACHE_OFF
59 struct dcache_config {
64 static void get_cache_ways_sets(struct dcache_config *cache)
66 u32 cache_size_id = readl(V7M_PROC_REG_CCSIDR);
68 cache->ways = (cache_size_id & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
69 cache->sets = (cache_size_id & MASK_NUM_SETS) >> NUM_SETS_SHIFT;
73 * Return the io register to perform required cache action like clean or clean
74 * & invalidate by sets/ways.
76 static u32 *get_action_reg_set_ways(enum cache_action action)
79 case INVALIDATE_SET_WAY:
80 return V7M_CACHE_REG_DCISW;
82 return V7M_CACHE_REG_DCCSW;
83 case FLUSH_INVAL_SET_WAY:
84 return V7M_CACHE_REG_DCCISW;
93 * Return the io register to perform required cache action like clean or clean
94 * & invalidate by adddress or range.
96 static u32 *get_action_reg_range(enum cache_action action)
100 return V7M_CACHE_REG_ICIMVALU;
102 return V7M_CACHE_REG_DCIMVAC;
104 return V7M_CACHE_REG_DCCMVAU;
106 return V7M_CACHE_REG_DCCMVAC;
107 case FLUSH_INVAL_POC:
108 return V7M_CACHE_REG_DCCIMVAC;
116 static u32 get_cline_size(enum cache_type type)
121 clrbits_le32(V7M_PROC_REG_CSSELR, BIT(SEL_I_OR_D));
122 else if (type == ICACHE)
123 setbits_le32(V7M_PROC_REG_CSSELR, BIT(SEL_I_OR_D));
124 /* Make sure cache selection is effective for next memory access */
127 size = readl(V7M_PROC_REG_CCSIDR) & CLINE_SIZE_MASK;
128 /* Size enocoded as 2 less than log(no_of_words_in_cache_line) base 2 */
129 size = 1 << (size + 2);
130 debug("cache line size is %d\n", size);
135 /* Perform the action like invalidate/clean on a range of cache addresses */
136 static int action_cache_range(enum cache_action action, u32 start_addr,
141 enum cache_type type;
143 action_reg = get_action_reg_range(action);
146 if (action == INVALIDATE_POU)
151 /* Cache line size is minium size for the cache action */
152 cline_size = get_cline_size(type);
153 /* Align start address to cache line boundary */
154 start_addr &= ~(cline_size - 1);
155 debug("total size for cache action = %llx\n", size);
157 writel(start_addr, action_reg);
159 start_addr += cline_size;
160 } while (size > cline_size);
162 /* Make sure cache action is effective for next memory access */
164 isb(); /* Make sure instruction stream sees it */
165 debug("cache action on range done\n");
170 /* Perform the action like invalidate/clean on all cached addresses */
171 static int action_dcache_all(enum cache_action action)
173 struct dcache_config cache;
177 action_reg = get_action_reg_set_ways(action);
181 clrbits_le32(V7M_PROC_REG_CSSELR, BIT(SEL_I_OR_D));
182 /* Make sure cache selection is effective for next memory access */
185 get_cache_ways_sets(&cache); /* Get number of ways & sets */
186 debug("cache: ways= %d, sets= %d\n", cache.ways + 1, cache.sets + 1);
187 for (i = cache.sets; i >= 0; i--) {
188 for (j = cache.ways; j >= 0; j--) {
189 writel((j << WAYS_SHIFT) | (i << SETS_SHIFT),
194 /* Make sure cache action is effective for next memory access */
196 isb(); /* Make sure instruction stream sees it */
201 void dcache_enable(void)
203 if (dcache_status()) /* return if cache already enabled */
206 if (action_dcache_all(INVALIDATE_SET_WAY)) {
207 printf("ERR: D-cache not enabled\n");
211 setbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_DCACHE));
213 /* Make sure cache action is effective for next memory access */
215 isb(); /* Make sure instruction stream sees it */
218 void dcache_disable(void)
220 if (!dcache_status())
223 /* if dcache is enabled-> dcache disable & then flush */
224 if (action_dcache_all(FLUSH_SET_WAY)) {
225 printf("ERR: D-cache not flushed\n");
229 clrbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_DCACHE));
231 /* Make sure cache action is effective for next memory access */
233 isb(); /* Make sure instruction stream sees it */
236 int dcache_status(void)
238 return (readl(&V7M_SCB->ccr) & BIT(V7M_CCR_DCACHE)) != 0;
241 void invalidate_dcache_range(unsigned long start, unsigned long stop)
243 if (action_cache_range(INVALIDATE_POC, start, stop - start)) {
244 printf("ERR: D-cache not invalidated\n");
249 void flush_dcache_range(unsigned long start, unsigned long stop)
251 if (action_cache_range(FLUSH_POC, start, stop - start)) {
252 printf("ERR: D-cache not flushed\n");
257 void dcache_enable(void)
262 void dcache_disable(void)
267 int dcache_status(void)
273 #ifndef CONFIG_SYS_ICACHE_OFF
275 void invalidate_icache_all(void)
277 writel(INVAL_ICACHE_POU, V7M_CACHE_REG_ICIALLU);
279 /* Make sure cache action is effective for next memory access */
281 isb(); /* Make sure instruction stream sees it */
284 void icache_enable(void)
289 invalidate_icache_all();
290 setbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_ICACHE));
292 /* Make sure cache action is effective for next memory access */
294 isb(); /* Make sure instruction stream sees it */
297 int icache_status(void)
299 return (readl(&V7M_SCB->ccr) & BIT(V7M_CCR_ICACHE)) != 0;
302 void icache_disable(void)
304 if (!icache_status())
307 isb(); /* flush pipeline */
308 clrbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_ICACHE));
309 isb(); /* subsequent instructions fetch see cache disable effect */
312 void icache_enable(void)
317 void icache_disable(void)
322 int icache_status(void)
328 void enable_caches(void)
330 #ifndef CONFIG_SYS_ICACHE_OFF
333 #ifndef CONFIG_SYS_DCACHE_OFF