2 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2012 Xilinx, Inc. All rights reserved.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/sys_proto.h>
10 #include <asm/arch/hardware.h>
12 void lowlevel_init(void)
16 int arch_cpu_init(void)
20 /* Device config APB, unlock the PCAP */
21 writel(0x757BDF0D, &devcfg_base->unlock);
22 writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
24 #if (CONFIG_SYS_SDRAM_BASE == 0)
25 /* remap DDR to zero, FILTERSTART */
26 writel(0, &scu_base->filter_start);
28 /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
29 writel(0x1F, &slcr_base->ocm_cfg);
30 /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
31 writel(0x0, &slcr_base->fpga_rst_ctrl);
32 /* Set urgent bits with register */
33 writel(0x0, &slcr_base->ddr_urgent_sel);
34 /* Urgent write, ports S2/S3 */
35 writel(0xC, &slcr_base->ddr_urgent);
43 void reset_cpu(ulong addr)
45 zynq_slcr_cpu_reset();