2 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2012 Xilinx, Inc. All rights reserved.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/sys_proto.h>
26 #include <asm/arch/hardware.h>
28 void lowlevel_init(void)
31 /* remap DDR to zero, FILTERSTART */
32 writel(0, &scu_base->filter_start);
34 /* Device config APB, unlock the PCAP */
35 writel(0x757BDF0D, &devcfg_base->unlock);
36 writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
38 /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
39 writel(0x1F, &slcr_base->ocm_cfg);
40 /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
41 writel(0x0, &slcr_base->fpga_rst_ctrl);
42 /* TZ_DDR_RAM, Set DDR trust zone non-secure */
43 writel(0xFFFFFFFF, &slcr_base->trust_zone);
44 /* Set urgent bits with register */
45 writel(0x0, &slcr_base->ddr_urgent_sel);
46 /* Urgent write, ports S2/S3 */
47 writel(0xC, &slcr_base->ddr_urgent);
52 void reset_cpu(ulong addr)
54 zynq_slcr_cpu_reset();