arch/arm/cpu/armv7/zynq/clk.c

   1 /*
   2  * Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
   3  * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <clk.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/hardware.h>
  12 #include <asm/arch/clk.h>
  13
  14 /* Board oscillator frequency */
  15 #ifndef CONFIG_ZYNQ_PS_CLK_FREQ
  16 # define CONFIG_ZYNQ_PS_CLK_FREQ        33333333UL
  17 #endif
  18
  19 /* Register bitfield defines */
  20 #define PLLCTRL_FBDIV_MASK      0x7f000
  21 #define PLLCTRL_FBDIV_SHIFT     12
  22 #define PLLCTRL_BPFORCE_MASK    (1 << 4)
  23 #define PLLCTRL_PWRDWN_MASK     2
  24 #define PLLCTRL_PWRDWN_SHIFT    1
  25 #define PLLCTRL_RESET_MASK      1
  26 #define PLLCTRL_RESET_SHIFT     0
  27
  28 #define ZYNQ_CLK_MAXDIV         0x3f
  29 #define CLK_CTRL_DIV1_SHIFT     20
  30 #define CLK_CTRL_DIV1_MASK      (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
  31 #define CLK_CTRL_DIV0_SHIFT     8
  32 #define CLK_CTRL_DIV0_MASK      (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
  33 #define CLK_CTRL_SRCSEL_SHIFT   4
  34 #define CLK_CTRL_SRCSEL_MASK    (0x3 << CLK_CTRL_SRCSEL_SHIFT)
  35
  36 #define CLK_CTRL_DIV2X_SHIFT    26
  37 #define CLK_CTRL_DIV2X_MASK     (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV2X_SHIFT)
  38 #define CLK_CTRL_DIV3X_SHIFT    20
  39 #define CLK_CTRL_DIV3X_MASK     (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV3X_SHIFT)
  40
  41 #define ZYNQ_CLKMUX_SEL_0       0
  42 #define ZYNQ_CLKMUX_SEL_1       1
  43 #define ZYNQ_CLKMUX_SEL_2       2
  44 #define ZYNQ_CLKMUX_SEL_3       3
  45
  46 DECLARE_GLOBAL_DATA_PTR;
  47
  48 struct clk;
  49
  50 /**
  51  * struct clk_ops:
  52  * @set_rate:   Function pointer to set_rate() implementation
  53  * @get_rate:   Function pointer to get_rate() implementation
  54  */
  55 struct clk_ops {
  56         int (*set_rate)(struct clk *clk, unsigned long rate);
  57         unsigned long (*get_rate)(struct clk *clk);
  58 };
  59
  60 /**
  61  * struct clk:
  62  * @name:       Clock name
  63  * @frequency:  Currenct frequency
  64  * @parent:     Parent clock
  65  * @flags:      Clock flags
  66  * @reg:        Clock control register
  67  * @ops:        Clock operations
  68  */
  69 struct clk {
  70         char            *name;
  71         unsigned long   frequency;
  72         enum zynq_clk   parent;
  73         unsigned int    flags;
  74         u32             *reg;
  75         struct clk_ops  ops;
  76 };
  77 #define ZYNQ_CLK_FLAGS_HAS_2_DIVS       1
  78
  79 static struct clk clks[clk_max];
  80
  81 /**
  82  * __zynq_clk_cpu_get_parent() - Decode clock multiplexer
  83  * @srcsel:     Mux select value
  84  * Returns the clock identifier associated with the selected mux input.
  85  */
  86 static int __zynq_clk_cpu_get_parent(unsigned int srcsel)
  87 {
  88         unsigned int ret;
  89
  90         switch (srcsel) {
  91         case ZYNQ_CLKMUX_SEL_0:
  92         case ZYNQ_CLKMUX_SEL_1:
  93                 ret = armpll_clk;
  94                 break;
  95         case ZYNQ_CLKMUX_SEL_2:
  96                 ret = ddrpll_clk;
  97                 break;
  98         case ZYNQ_CLKMUX_SEL_3:
  99                 ret = iopll_clk;
 100                 break;
 101         default:
 102                 ret = armpll_clk;
 103                 break;
 104         }
 105
 106         return ret;
 107 }
 108
 109 /**
 110  * ddr2x_get_rate() - Get clock rate of DDR2x clock
 111  * @clk:        Clock handle
 112  * Returns the current clock rate of @clk.
 113  */
 114 static unsigned long ddr2x_get_rate(struct clk *clk)
 115 {
 116         u32 clk_ctrl = readl(clk->reg);
 117         u32 div = (clk_ctrl & CLK_CTRL_DIV2X_MASK) >> CLK_CTRL_DIV2X_SHIFT;
 118
 119         return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
 120 }
 121
 122 /**
 123  * ddr3x_get_rate() - Get clock rate of DDR3x clock
 124  * @clk:        Clock handle
 125  * Returns the current clock rate of @clk.
 126  */
 127 static unsigned long ddr3x_get_rate(struct clk *clk)
 128 {
 129         u32 clk_ctrl = readl(clk->reg);
 130         u32 div = (clk_ctrl & CLK_CTRL_DIV3X_MASK) >> CLK_CTRL_DIV3X_SHIFT;
 131
 132         return DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div);
 133 }
 134
 135 static void init_ddr_clocks(void)
 136 {
 137         u32 div0, div1;
 138         unsigned long prate = zynq_clk_get_rate(ddrpll_clk);
 139         u32 clk_ctrl = readl(&slcr_base->ddr_clk_ctrl);
 140
 141         /* DDR2x */
 142         clks[ddr2x_clk].reg = &slcr_base->ddr_clk_ctrl;
 143         clks[ddr2x_clk].parent = ddrpll_clk;
 144         clks[ddr2x_clk].name = "ddr_2x";
 145         clks[ddr2x_clk].frequency = ddr2x_get_rate(&clks[ddr2x_clk]);
 146         clks[ddr2x_clk].ops.get_rate = ddr2x_get_rate;
 147
 148         /* DDR3x */
 149         clks[ddr3x_clk].reg = &slcr_base->ddr_clk_ctrl;
 150         clks[ddr3x_clk].parent = ddrpll_clk;
 151         clks[ddr3x_clk].name = "ddr_3x";
 152         clks[ddr3x_clk].frequency = ddr3x_get_rate(&clks[ddr3x_clk]);
 153         clks[ddr3x_clk].ops.get_rate = ddr3x_get_rate;
 154
 155         /* DCI */
 156         clk_ctrl = readl(&slcr_base->dci_clk_ctrl);
 157         div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 158         div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
 159         clks[dci_clk].reg = &slcr_base->dci_clk_ctrl;
 160         clks[dci_clk].parent = ddrpll_clk;
 161         clks[dci_clk].frequency = DIV_ROUND_CLOSEST(
 162                         DIV_ROUND_CLOSEST(prate, div0), div1);
 163         clks[dci_clk].name = "dci";
 164 }
 165
 166 static void init_cpu_clocks(void)
 167 {
 168         int clk_621;
 169         u32 reg, div, srcsel;
 170         enum zynq_clk parent;
 171
 172         reg = readl(&slcr_base->arm_clk_ctrl);
 173         clk_621 = readl(&slcr_base->clk_621_true) & 1;
 174         div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 175         srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
 176         parent = __zynq_clk_cpu_get_parent(srcsel);
 177
 178         /* cpu clocks */
 179         clks[cpu_6or4x_clk].reg = &slcr_base->arm_clk_ctrl;
 180         clks[cpu_6or4x_clk].parent = parent;
 181         clks[cpu_6or4x_clk].frequency = DIV_ROUND_CLOSEST(
 182                         zynq_clk_get_rate(parent), div);
 183         clks[cpu_6or4x_clk].name = "cpu_6or4x";
 184
 185         clks[cpu_3or2x_clk].reg = &slcr_base->arm_clk_ctrl;
 186         clks[cpu_3or2x_clk].parent = cpu_6or4x_clk;
 187         clks[cpu_3or2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) / 2;
 188         clks[cpu_3or2x_clk].name = "cpu_3or2x";
 189
 190         clks[cpu_2x_clk].reg = &slcr_base->arm_clk_ctrl;
 191         clks[cpu_2x_clk].parent = cpu_6or4x_clk;
 192         clks[cpu_2x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
 193                         (2 + clk_621);
 194         clks[cpu_2x_clk].name = "cpu_2x";
 195
 196         clks[cpu_1x_clk].reg = &slcr_base->arm_clk_ctrl;
 197         clks[cpu_1x_clk].parent = cpu_6or4x_clk;
 198         clks[cpu_1x_clk].frequency = zynq_clk_get_rate(cpu_6or4x_clk) /
 199                         (4 + 2 * clk_621);
 200         clks[cpu_1x_clk].name = "cpu_1x";
 201 }
 202
 203 /**
 204  * periph_calc_two_divs() - Calculate clock dividers
 205  * @cur_rate:   Current clock rate
 206  * @tgt_rate:   Target clock rate
 207  * @prate:      Parent clock rate
 208  * @div0:       First divider (output)
 209  * @div1:       Second divider (output)
 210  * Returns the actual clock rate possible.
 211  *
 212  * Calculates clock dividers for clocks with two 6-bit dividers.
 213  */
 214 static unsigned long periph_calc_two_divs(unsigned long cur_rate,
 215                 unsigned long tgt_rate, unsigned long prate, u32 *div0,
 216                 u32 *div1)
 217 {
 218         long err, best_err = (long)(~0UL >> 1);
 219         unsigned long rate, best_rate = 0;
 220         u32 d0, d1;
 221
 222         for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
 223                 for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
 224                         rate = DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(prate, d0),
 225                                         d1);
 226                         err = abs(rate - tgt_rate);
 227
 228                         if (err < best_err) {
 229                                 *div0 = d0;
 230                                 *div1 = d1;
 231                                 best_err = err;
 232                                 best_rate = rate;
 233                         }
 234                 }
 235         }
 236
 237         return best_rate;
 238 }
 239
 240 /**
 241  * zynq_clk_periph_set_rate() - Set clock rate
 242  * @clk:        Handle of the peripheral clock
 243  * @rate:       New clock rate
 244  * Sets the clock frequency of @clk to @rate. Returns zero on success.
 245  */
 246 static int zynq_clk_periph_set_rate(struct clk *clk,
 247                 unsigned long rate)
 248 {
 249         u32 ctrl, div0 = 0, div1 = 0;
 250         unsigned long prate, new_rate, cur_rate = clk->frequency;
 251
 252         ctrl = readl(clk->reg);
 253         prate = zynq_clk_get_rate(clk->parent);
 254         ctrl &= ~CLK_CTRL_DIV0_MASK;
 255
 256         if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS) {
 257                 ctrl &= ~CLK_CTRL_DIV1_MASK;
 258                 new_rate = periph_calc_two_divs(cur_rate, rate, prate, &div0,
 259                                 &div1);
 260                 ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;
 261         } else {
 262                 div0 = DIV_ROUND_CLOSEST(prate, rate);
 263                 div0 &= ZYNQ_CLK_MAXDIV;
 264                 new_rate = DIV_ROUND_CLOSEST(rate, div0);
 265         }
 266
 267         /* write new divs to hardware */
 268         ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;
 269         writel(ctrl, clk->reg);
 270
 271         /* update frequency in clk framework */
 272         clk->frequency = new_rate;
 273
 274         return 0;
 275 }
 276
 277 /**
 278  * zynq_clk_periph_get_rate() - Get clock rate
 279  * @clk:        Handle of the peripheral clock
 280  * Returns the current clock rate of @clk.
 281  */
 282 static unsigned long zynq_clk_periph_get_rate(struct clk *clk)
 283 {
 284         u32 clk_ctrl = readl(clk->reg);
 285         u32 div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 286         u32 div1 = 1;
 287
 288         if (clk->flags & ZYNQ_CLK_FLAGS_HAS_2_DIVS)
 289                 div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
 290
 291         /* a register value of zero == division by 1 */
 292         if (!div0)
 293                 div0 = 1;
 294         if (!div1)
 295                 div1 = 1;
 296
 297         return
 298                 DIV_ROUND_CLOSEST(
 299                         DIV_ROUND_CLOSEST(zynq_clk_get_rate(clk->parent), div0),
 300                         div1);
 301 }
 302
 303 /**
 304  * __zynq_clk_periph_get_parent() - Decode clock multiplexer
 305  * @srcsel:     Mux select value
 306  * Returns the clock identifier associated with the selected mux input.
 307  */
 308 static enum zynq_clk __zynq_clk_periph_get_parent(u32 srcsel)
 309 {
 310         switch (srcsel) {
 311         case ZYNQ_CLKMUX_SEL_0:
 312         case ZYNQ_CLKMUX_SEL_1:
 313                 return iopll_clk;
 314         case ZYNQ_CLKMUX_SEL_2:
 315                 return armpll_clk;
 316         case ZYNQ_CLKMUX_SEL_3:
 317                 return ddrpll_clk;
 318         default:
 319                 return 0;
 320         }
 321 }
 322
 323 /**
 324  * zynq_clk_periph_get_parent() - Decode clock multiplexer
 325  * @clk:        Clock handle
 326  * Returns the clock identifier associated with the selected mux input.
 327  */
 328 static enum zynq_clk zynq_clk_periph_get_parent(struct clk *clk)
 329 {
 330         u32 clk_ctrl = readl(clk->reg);
 331         u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
 332
 333         return __zynq_clk_periph_get_parent(srcsel);
 334 }
 335
 336 /**
 337  * zynq_clk_register_periph_clk() - Set up a peripheral clock with the framework
 338  * @clk:        Pointer to struct clk for the clock
 339  * @ctrl:       Clock control register
 340  * @name:       PLL name
 341  * @two_divs:   Indicates whether the clock features one or two dividers
 342  */
 343 static int zynq_clk_register_periph_clk(struct clk *clk, u32 *ctrl, char *name,
 344                 bool two_divs)
 345 {
 346         clk->name = name;
 347         clk->reg = ctrl;
 348         if (two_divs)
 349                 clk->flags = ZYNQ_CLK_FLAGS_HAS_2_DIVS;
 350         clk->parent = zynq_clk_periph_get_parent(clk);
 351         clk->frequency = zynq_clk_periph_get_rate(clk);
 352         clk->ops.get_rate = zynq_clk_periph_get_rate;
 353         clk->ops.set_rate = zynq_clk_periph_set_rate;
 354
 355         return 0;
 356 }
 357
 358 static void init_periph_clocks(void)
 359 {
 360         zynq_clk_register_periph_clk(&clks[gem0_clk], &slcr_base->gem0_clk_ctrl,
 361                                      "gem0", 1);
 362         zynq_clk_register_periph_clk(&clks[gem1_clk], &slcr_base->gem1_clk_ctrl,
 363                                      "gem1", 1);
 364
 365         zynq_clk_register_periph_clk(&clks[smc_clk], &slcr_base->smc_clk_ctrl,
 366                                      "smc", 0);
 367
 368         zynq_clk_register_periph_clk(&clks[lqspi_clk],
 369                                      &slcr_base->lqspi_clk_ctrl, "lqspi", 0);
 370
 371         zynq_clk_register_periph_clk(&clks[sdio0_clk],
 372                                      &slcr_base->sdio_clk_ctrl, "sdio0", 0);
 373         zynq_clk_register_periph_clk(&clks[sdio1_clk],
 374                                      &slcr_base->sdio_clk_ctrl, "sdio1", 0);
 375
 376         zynq_clk_register_periph_clk(&clks[spi0_clk], &slcr_base->spi_clk_ctrl,
 377                                      "spi0", 0);
 378         zynq_clk_register_periph_clk(&clks[spi1_clk], &slcr_base->spi_clk_ctrl,
 379                                      "spi1", 0);
 380
 381         zynq_clk_register_periph_clk(&clks[uart0_clk],
 382                                      &slcr_base->uart_clk_ctrl, "uart0", 0);
 383         zynq_clk_register_periph_clk(&clks[uart1_clk],
 384                                      &slcr_base->uart_clk_ctrl, "uart1", 0);
 385
 386         zynq_clk_register_periph_clk(&clks[dbg_trc_clk],
 387                                      &slcr_base->dbg_clk_ctrl, "dbg_trc", 0);
 388         zynq_clk_register_periph_clk(&clks[dbg_apb_clk],
 389                                      &slcr_base->dbg_clk_ctrl, "dbg_apb", 0);
 390
 391         zynq_clk_register_periph_clk(&clks[pcap_clk],
 392                                      &slcr_base->pcap_clk_ctrl, "pcap", 0);
 393
 394         zynq_clk_register_periph_clk(&clks[fclk0_clk],
 395                                      &slcr_base->fpga0_clk_ctrl, "fclk0", 1);
 396         zynq_clk_register_periph_clk(&clks[fclk1_clk],
 397                                      &slcr_base->fpga1_clk_ctrl, "fclk1", 1);
 398         zynq_clk_register_periph_clk(&clks[fclk2_clk],
 399                                      &slcr_base->fpga2_clk_ctrl, "fclk2", 1);
 400         zynq_clk_register_periph_clk(&clks[fclk3_clk],
 401                                      &slcr_base->fpga3_clk_ctrl, "fclk3", 1);
 402 }
 403
 404 /**
 405  * zynq_clk_register_aper_clk() - Set up a APER clock with the framework
 406  * @clk:        Pointer to struct clk for the clock
 407  * @ctrl:       Clock control register
 408  * @name:       PLL name
 409  */
 410 static void zynq_clk_register_aper_clk(struct clk *clk, u32 *ctrl, char *name)
 411 {
 412         clk->name = name;
 413         clk->reg = ctrl;
 414         clk->parent = cpu_1x_clk;
 415         clk->frequency = zynq_clk_get_rate(clk->parent);
 416 }
 417
 418 static void init_aper_clocks(void)
 419 {
 420         zynq_clk_register_aper_clk(&clks[usb0_aper_clk],
 421                                    &slcr_base->aper_clk_ctrl, "usb0_aper");
 422         zynq_clk_register_aper_clk(&clks[usb1_aper_clk],
 423                                    &slcr_base->aper_clk_ctrl, "usb1_aper");
 424
 425         zynq_clk_register_aper_clk(&clks[gem0_aper_clk],
 426                                    &slcr_base->aper_clk_ctrl, "gem0_aper");
 427         zynq_clk_register_aper_clk(&clks[gem1_aper_clk],
 428                                    &slcr_base->aper_clk_ctrl, "gem1_aper");
 429
 430         zynq_clk_register_aper_clk(&clks[sdio0_aper_clk],
 431                                    &slcr_base->aper_clk_ctrl, "sdio0_aper");
 432         zynq_clk_register_aper_clk(&clks[sdio1_aper_clk],
 433                                    &slcr_base->aper_clk_ctrl, "sdio1_aper");
 434
 435         zynq_clk_register_aper_clk(&clks[spi0_aper_clk],
 436                                    &slcr_base->aper_clk_ctrl, "spi0_aper");
 437         zynq_clk_register_aper_clk(&clks[spi1_aper_clk],
 438                                    &slcr_base->aper_clk_ctrl, "spi1_aper");
 439
 440         zynq_clk_register_aper_clk(&clks[can0_aper_clk],
 441                                    &slcr_base->aper_clk_ctrl, "can0_aper");
 442         zynq_clk_register_aper_clk(&clks[can1_aper_clk],
 443                                    &slcr_base->aper_clk_ctrl, "can1_aper");
 444
 445         zynq_clk_register_aper_clk(&clks[i2c0_aper_clk],
 446                                    &slcr_base->aper_clk_ctrl, "i2c0_aper");
 447         zynq_clk_register_aper_clk(&clks[i2c1_aper_clk],
 448                                    &slcr_base->aper_clk_ctrl, "i2c1_aper");
 449
 450         zynq_clk_register_aper_clk(&clks[uart0_aper_clk],
 451                                    &slcr_base->aper_clk_ctrl, "uart0_aper");
 452         zynq_clk_register_aper_clk(&clks[uart1_aper_clk],
 453                                    &slcr_base->aper_clk_ctrl, "uart1_aper");
 454
 455         zynq_clk_register_aper_clk(&clks[gpio_aper_clk],
 456                                    &slcr_base->aper_clk_ctrl, "gpio_aper");
 457
 458         zynq_clk_register_aper_clk(&clks[lqspi_aper_clk],
 459                                    &slcr_base->aper_clk_ctrl, "lqspi_aper");
 460
 461         zynq_clk_register_aper_clk(&clks[smc_aper_clk],
 462                                    &slcr_base->aper_clk_ctrl, "smc_aper");
 463 }
 464
 465 /**
 466  * __zynq_clk_pll_get_rate() - Get PLL rate
 467  * @addr:       Address of the PLL's control register
 468  * Returns the current PLL output rate.
 469  */
 470 static unsigned long __zynq_clk_pll_get_rate(u32 *addr)
 471 {
 472         u32 reg, mul, bypass;
 473
 474         reg = readl(addr);
 475         bypass = reg & PLLCTRL_BPFORCE_MASK;
 476         if (bypass)
 477                 mul = 1;
 478         else
 479                 mul = (reg & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
 480
 481         return CONFIG_ZYNQ_PS_CLK_FREQ * mul;
 482 }
 483
 484 /**
 485  * zynq_clk_pll_get_rate() - Get PLL rate
 486  * @pll:        Handle of the PLL
 487  * Returns the current clock rate of @pll.
 488  */
 489 static unsigned long zynq_clk_pll_get_rate(struct clk *pll)
 490 {
 491         return __zynq_clk_pll_get_rate(pll->reg);
 492 }
 493
 494 /**
 495  * zynq_clk_register_pll() - Set up a PLL with the framework
 496  * @clk:        Pointer to struct clk for the PLL
 497  * @ctrl:       PLL control register
 498  * @name:       PLL name
 499  * @prate:      PLL input clock rate
 500  */
 501 static void zynq_clk_register_pll(struct clk *clk, u32 *ctrl, char *name,
 502                 unsigned long prate)
 503 {
 504         clk->name = name;
 505         clk->reg = ctrl;
 506         clk->frequency = zynq_clk_pll_get_rate(clk);
 507         clk->ops.get_rate = zynq_clk_pll_get_rate;
 508 }
 509
 510 /**
 511  * clkid_2_register() - Get clock control register
 512  * @id: Clock identifier of one of the PLLs
 513  * Returns the address of the requested PLL's control register.
 514  */
 515 static u32 *clkid_2_register(enum zynq_clk id)
 516 {
 517         switch (id) {
 518         case armpll_clk:
 519                 return &slcr_base->arm_pll_ctrl;
 520         case ddrpll_clk:
 521                 return &slcr_base->ddr_pll_ctrl;
 522         case iopll_clk:
 523                 return &slcr_base->io_pll_ctrl;
 524         default:
 525                 return &slcr_base->io_pll_ctrl;
 526         }
 527 }
 528
 529 /* API */
 530 /**
 531  * zynq_clk_early_init() - Early init for the clock framework
 532  *
 533  * This function is called from before relocation and sets up the CPU clock
 534  * frequency in the global data struct.
 535  */
 536 void zynq_clk_early_init(void)
 537 {
 538         u32 reg = readl(&slcr_base->arm_clk_ctrl);
 539         u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 540         u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
 541         enum zynq_clk parent = __zynq_clk_cpu_get_parent(srcsel);
 542         u32 *pllreg = clkid_2_register(parent);
 543         unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
 544
 545         if (!div)
 546                 div = 1;
 547
 548         gd->cpu_clk = DIV_ROUND_CLOSEST(prate, div);
 549 }
 550
 551 /**
 552  * get_uart_clk() - Get UART input frequency
 553  * @dev_index:  UART ID
 554  * Returns UART input clock frequency in Hz.
 555  *
 556  * Compared to zynq_clk_get_rate() this function is designed to work before
 557  * relocation and can be called when the serial UART is set up.
 558  */
 559 unsigned long get_uart_clk(int dev_index)
 560 {
 561         u32 reg = readl(&slcr_base->uart_clk_ctrl);
 562         u32 div = (reg & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
 563         u32 srcsel = (reg & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
 564         enum zynq_clk parent = __zynq_clk_periph_get_parent(srcsel);
 565         u32 *pllreg = clkid_2_register(parent);
 566         unsigned long prate = __zynq_clk_pll_get_rate(pllreg);
 567
 568         if (!div)
 569                 div = 1;
 570
 571         return DIV_ROUND_CLOSEST(prate, div);
 572 }
 573
 574 /**
 575  * set_cpu_clk_info() - Initialize clock framework
 576  * Always returns zero.
 577  *
 578  * This function is called from common code after relocation and sets up the
 579  * clock framework. The framework must not be used before this function had been
 580  * called.
 581  */
 582 int set_cpu_clk_info(void)
 583 {
 584         zynq_clk_register_pll(&clks[armpll_clk], &slcr_base->arm_pll_ctrl,
 585                               "armpll", CONFIG_ZYNQ_PS_CLK_FREQ);
 586         zynq_clk_register_pll(&clks[ddrpll_clk], &slcr_base->ddr_pll_ctrl,
 587                               "ddrpll", CONFIG_ZYNQ_PS_CLK_FREQ);
 588         zynq_clk_register_pll(&clks[iopll_clk], &slcr_base->io_pll_ctrl,
 589                               "iopll", CONFIG_ZYNQ_PS_CLK_FREQ);
 590
 591         init_ddr_clocks();
 592         init_cpu_clocks();
 593         init_periph_clocks();
 594         init_aper_clocks();
 595
 596         return 0;
 597 }
 598
 599 /**
 600  * zynq_clk_get_rate() - Get clock rate
 601  * @clk:        Clock identifier
 602  * Returns the current clock rate of @clk on success or zero for an invalid
 603  * clock id.
 604  */
 605 unsigned long zynq_clk_get_rate(enum zynq_clk clk)
 606 {
 607         if (clk < 0 || clk >= clk_max)
 608                 return 0;
 609
 610         return clks[clk].frequency;
 611 }
 612
 613 /**
 614  * zynq_clk_set_rate() - Set clock rate
 615  * @clk:        Clock identifier
 616  * @rate:       Requested clock rate
 617  * Passes on the return value from the clock's set_rate() function or negative
 618  * errno.
 619  */
 620 int zynq_clk_set_rate(enum zynq_clk clk, unsigned long rate)
 621 {
 622         if (clk < 0 || clk >= clk_max)
 623                 return -ENODEV;
 624
 625         if (clks[clk].ops.set_rate)
 626                 return clks[clk].ops.set_rate(&clks[clk], rate);
 627
 628         return -ENXIO;
 629 }
 630
 631 /**
 632  * zynq_clk_get_name() - Get clock name
 633  * @clk:        Clock identifier
 634  * Returns the name of @clk.
 635  */
 636 const char *zynq_clk_get_name(enum zynq_clk clk)
 637 {
 638         return clks[clk].name;
 639 }
 640
 641 /**
 642  * soc_clk_dump() - Print clock frequencies
 643  * Returns zero on success
 644  *
 645  * Implementation for the clk dump command.
 646  */
 647 int soc_clk_dump(void)
 648 {
 649         int i;
 650
 651         printf("clk\t\tfrequency\n");
 652         for (i = 0; i < clk_max; i++) {
 653                 const char *name = zynq_clk_get_name(i);
 654                 if (name)
 655                         printf("%10s%20lu\n", name, zynq_clk_get_rate(i));
 656         }
 657
 658         return 0;
 659 }