2 * Copyright (c) 2011 The Chromium OS Authors.
3 * See file CREDITS for list of people who contributed to this
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 /* Tegra2 pin multiplexing functions */
25 #include <asm/arch/tegra2.h>
26 #include <asm/arch/pinmux.h>
31 * This defines the order of the pin mux control bits in the registers. For
32 * some reason there is no correspendence between the tristate, pin mux and
33 * pullup/pulldown registers.
36 /* 0: APB_MISC_PP_PIN_MUX_CTL_A_0 */
55 /* 16: APB_MISC_PP_PIN_MUX_CTL_B_0 */
74 /* 32: APB_MISC_PP_PIN_MUX_CTL_C_0 */
93 /* 48: APB_MISC_PP_PIN_MUX_CTL_D_0 */
112 /* 64: APB_MISC_PP_PIN_MUX_CTL_E_0 */
131 /* 80: APB_MISC_PP_PIN_MUX_CTL_F_0 */
150 /* 96: APB_MISC_PP_PIN_MUX_CTL_G_0 */
173 * And this defines the order of the pullup/pulldown controls which are again
174 * in a different order
177 /* 0: APB_MISC_PP_PULLUPDOWN_REG_A_0 */
196 /* 16: APB_MISC_PP_PULLUPDOWN_REG_B_0 */
214 /* 32: APB_MISC_PP_PULLUPDOWN_REG_C_0 */
233 /* 48: APB_MISC_PP_PULLUPDOWN_REG_D_0 */
252 /* 64: APB_MISC_PP_PULLUPDOWN_REG_E_0 */
274 struct tegra_pingroup_desc {
276 enum pmux_func funcs[4];
277 enum pmux_func func_safe;
278 enum pmux_vddio vddio;
279 enum pmux_ctlid ctl_id;
280 enum pmux_pullid pull_id;
284 /* Converts a pmux_pingrp number to a tristate register: 0=A, 1=B, 2=C, 3=D */
285 #define TRISTATE_REG(pmux_pingrp) ((pmux_pingrp) >> 5)
287 /* Mask value for a tristate (within TRISTATE_REG(id)) */
288 #define TRISTATE_MASK(pmux_pingrp) (1 << ((pmux_pingrp) & 0x1f))
290 /* Converts a PUCTL id to a pull register: 0=A, 1=B...4=E */
291 #define PULL_REG(pmux_pullid) ((pmux_pullid) >> 4)
293 /* Converts a PUCTL id to a shift position */
294 #define PULL_SHIFT(pmux_pullid) ((pmux_pullid << 1) & 0x1f)
296 /* Converts a MUXCTL id to a ctl register: 0=A, 1=B...6=G */
297 #define MUXCTL_REG(pmux_ctlid) ((pmux_ctlid) >> 4)
299 /* Converts a MUXCTL id to a shift position */
300 #define MUXCTL_SHIFT(pmux_ctlid) ((pmux_ctlid << 1) & 0x1f)
302 /* Convenient macro for defining pin group properties */
303 #define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd) \
305 .vddio = PMUX_VDDIO_ ## vdd, \
312 .func_safe = PMUX_FUNC_ ## f_safe, \
317 /* A normal pin group where the mux name and pull-up name match */
318 #define PIN(pg_name, vdd, f0, f1, f2, f3, f_safe) \
319 PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
320 MUXCTL_ ## pg_name, PUCTL_ ## pg_name)
322 /* A pin group where the pull-up name doesn't have a 1-1 mapping */
323 #define PINP(pg_name, vdd, f0, f1, f2, f3, f_safe, pupd) \
324 PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
325 MUXCTL_ ## pg_name, PUCTL_ ## pupd)
327 /* A pin group number which is not used */
328 #define PIN_RESERVED \
329 PIN(NONE, NONE, NONE, NONE, NONE, NONE, NONE)
331 const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
332 PIN(ATA, NAND, IDE, NAND, GMI, RSVD, IDE),
333 PIN(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE),
334 PIN(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE),
335 PIN(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE),
336 PIN(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC),
337 PIN(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC),
338 PIN(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK,
340 PIN(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1),
342 PIN(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2),
343 PIN(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3),
344 PIN(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4),
345 PIN(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4),
346 PIN(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1),
347 PIN(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1),
348 PIN(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1),
349 PIN(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1),
351 PINP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4,
353 PIN(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE),
354 PIN(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4),
355 PIN(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
356 PIN(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
357 PIN(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC),
358 PIN(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC),
359 PINP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, NONE),
361 PIN(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4),
362 PIN(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4),
363 PIN(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC),
364 PIN(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC),
365 PIN(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3),
366 PIN(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4),
367 PIN(SDMMC1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2),
368 PIN(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR),
370 PIN(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI),
371 PIN(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC),
372 PIN(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM),
374 PINP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, CRTP),
375 PIN(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
376 PIN(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
377 PIN(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE),
379 PIN(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
380 PIN(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
381 PIN(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
382 PIN(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
383 PIN(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
384 PIN(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
385 PIN(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
386 PIN(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4),
388 PIN(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
389 PIN(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
390 PIN(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS),
391 PIN(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS),
392 PIN(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4),
393 PIN(UAD, UART, IRDA, SPDIF, UARTA, SPI4, SPDIF),
394 PIN(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4),
395 PIN(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4),
398 PIN(ATE, NAND, IDE, NAND, GMI, RSVD, IDE),
399 PIN(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC),
402 PIN(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI),
403 PIN(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI),
404 PIN(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4),
407 PINP(LD0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
408 PINP(LD1, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
409 PINP(LD2, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
410 PINP(LD3, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
411 PINP(LD4, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
412 PINP(LD5, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
413 PINP(LD6, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
414 PINP(LD7, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
416 PINP(LD8, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
417 PINP(LD9, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
418 PINP(LD10, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
419 PINP(LD11, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
420 PINP(LD12, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
421 PINP(LD13, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
422 PINP(LD14, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
423 PINP(LD15, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
425 PINP(LD16, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
426 PINP(LD17, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD17),
427 PINP(LHP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
428 PINP(LHP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
429 PINP(LHP2, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
430 PINP(LVP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LC),
431 PINP(LVP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
432 PINP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI , LC),
434 PINP(LM0, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LC),
435 PINP(LM1, LCD, DISPA, DISPB, RSVD, CRT, RSVD3, LC),
436 PINP(LVS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
437 PINP(LSC0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
438 PINP(LSC1, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
439 PINP(LSCK, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
440 PINP(LDC, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
441 PINP(LCSN, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LS),
444 PINP(LSPI, LCD, DISPA, DISPB, XIO, HDMI, DISPA, LC),
445 PINP(LSDA, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
446 PINP(LSDI, LCD, DISPA, DISPB, SPI3, RSVD, DISPA, LS),
447 PINP(LPW0, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
448 PINP(LPW1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
449 PINP(LPW2, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
450 PINP(LDI, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
451 PINP(LHS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
453 PINP(LPP, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
455 PIN(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC),
456 PIN(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK),
457 PIN(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4),
458 PIN(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2),
459 PIN(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD),
460 PINP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, NONE),
462 /* these pin groups only have pullup and pull down control */
463 PINALL(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
465 PINALL(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
467 PINALL(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
469 PINALL(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
471 PINALL(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
473 PINALL(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
475 PINALL(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
477 PINALL(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
479 PINALL(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
483 void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
485 struct pmux_tri_ctlr *pmt =
486 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
487 u32 *tri = &pmt->pmt_tri[TRISTATE_REG(pin)];
492 reg |= TRISTATE_MASK(pin);
494 reg &= ~TRISTATE_MASK(pin);
498 void pinmux_tristate_enable(enum pmux_pingrp pin)
500 pinmux_set_tristate(pin, 1);
503 void pinmux_tristate_disable(enum pmux_pingrp pin)
505 pinmux_set_tristate(pin, 0);
508 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
510 struct pmux_tri_ctlr *pmt =
511 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
512 enum pmux_pullid pull_id = tegra_soc_pingroups[pin].pull_id;
513 u32 *pull = &pmt->pmt_pull[PULL_REG(pull_id)];
516 mask_bit = PULL_SHIFT(pull_id);
519 reg &= ~(0x3 << mask_bit);
520 reg |= pupd << mask_bit;
524 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
526 struct pmux_tri_ctlr *pmt =
527 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
528 enum pmux_ctlid mux_id = tegra_soc_pingroups[pin].ctl_id;
529 u32 *muxctl = &pmt->pmt_ctl[MUXCTL_REG(mux_id)];
534 assert(pmux_func_isvalid(func));
536 /* Handle special values */
537 if (func >= PMUX_FUNC_RSVD1) {
538 mux = (func - PMUX_FUNC_RSVD1) & 0x3;
540 /* Search for the appropriate function */
541 for (i = 0; i < 4; i++) {
542 if (tegra_soc_pingroups[pin].funcs[i] == func) {
550 mask_bit = MUXCTL_SHIFT(mux_id);
552 reg &= ~(0x3 << mask_bit);
553 reg |= mux << mask_bit;
557 void pinmux_config_pingroup(struct pingroup_config *config)
559 enum pmux_pingrp pin = config->pingroup;
561 pinmux_set_func(pin, config->func);
562 pinmux_set_pullupdown(pin, config->pull);
563 pinmux_set_tristate(pin, config->tristate);
566 void pinmux_config_table(struct pingroup_config *config, int len)
570 for (i = 0; i < len; i++)
571 pinmux_config_pingroup(&config[i]);