2 * Copyright (c) 2011 The Chromium OS Authors.
3 * See file CREDITS for list of people who contributed to this
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 /* Tegra2 Clock control functions */
25 #include <asm/arch/clk_rst.h>
26 #include <asm/arch/clock.h>
27 #include <asm/arch/timer.h>
28 #include <asm/arch/tegra2.h>
34 * This is our record of the current clock rate of each clock. We don't
35 * fill all of these in since we are only really interested in clocks which
38 static unsigned pll_rate[CLOCK_ID_COUNT];
41 * The oscillator frequency is fixed to one of four set values. Based on this
42 * the other clocks are set up appropriately.
44 static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
52 * Clock types that we can use as a source. The Tegra2 has muxes for the
53 * peripheral clocks, and in most cases there are four options for the clock
54 * source. This gives us a clock 'type' and exploits what commonality exists
57 * Letters are obvious, except for T which means CLK_M, and S which means the
58 * clock derived from 32KHz. Beware that CLK_M (also called OSC in the
59 * datasheet) and PLL_M are different things. The former is the basic
60 * clock supplied to the SOC from an external oscillator. The latter is the
63 * See definitions in clock_id in the header file.
66 CLOCK_TYPE_AXPT, /* PLL_A, PLL_X, PLL_P, CLK_M */
67 CLOCK_TYPE_MCPA, /* and so on */
75 CLOCK_TYPE_NONE = -1, /* invalid clock type */
78 /* return 1 if a peripheral ID is in range */
79 #define clock_type_id_isvalid(id) ((id) >= 0 && \
80 (id) < CLOCK_TYPE_COUNT)
82 char pllp_valid = 1; /* PLLP is set up correctly */
85 CLOCK_MAX_MUX = 4 /* number of source options for each clock */
89 * Clock source mux for each clock type. This just converts our enum into
90 * a list of mux sources for use by the code. Note that CLOCK_TYPE_PCXTS
91 * is special as it has 5 sources. Since it also has a different number of
92 * bits in its register for the source, we just handle it with a special
95 #define CLK(x) CLOCK_ID_ ## x
96 static enum clock_id clock_source[CLOCK_TYPE_COUNT][CLOCK_MAX_MUX] = {
97 { CLK(AUDIO), CLK(XCPU), CLK(PERIPH), CLK(OSC) },
98 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(AUDIO) },
99 { CLK(MEMORY), CLK(CGENERAL), CLK(PERIPH), CLK(OSC) },
100 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(NONE) },
101 { CLK(PERIPH), CLK(CGENERAL), CLK(MEMORY), CLK(OSC) },
102 { CLK(PERIPH), CLK(CGENERAL), CLK(XCPU), CLK(OSC) },
103 { CLK(PERIPH), CLK(DISPLAY), CLK(CGENERAL), CLK(OSC) },
107 * Clock peripheral IDs which sadly don't match up with PERIPH_ID. This is
108 * not in the header file since it is for purely internal use - we want
109 * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
110 * confusion bewteen PERIPH_ID_... and PERIPHC_...
112 * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
115 * Note to SOC vendors: perhaps define a unified numbering for peripherals and
116 * use it for reset, clock enable, clock source/divider and even pinmuxing
119 enum periphc_internal_id {
136 PERIPHC_10, /* PERIPHC_SPI1, what is this really? */
193 /* return 1 if a periphc_internal_id is in range */
194 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \
195 (id) < PERIPHC_COUNT)
198 * Clock type for each peripheral clock source. We put the name in each
199 * record just so it is easy to match things up
201 #define TYPE(name, type) type
202 static enum clock_type_id clock_periph_type[PERIPHC_COUNT] = {
204 TYPE(PERIPHC_I2S1, CLOCK_TYPE_AXPT),
205 TYPE(PERIPHC_I2S2, CLOCK_TYPE_AXPT),
206 TYPE(PERIPHC_SPDIF_OUT, CLOCK_TYPE_AXPT),
207 TYPE(PERIPHC_SPDIF_IN, CLOCK_TYPE_PCM),
208 TYPE(PERIPHC_PWM, CLOCK_TYPE_PCXTS),
209 TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
210 TYPE(PERIPHC_SPI22, CLOCK_TYPE_PCMT),
211 TYPE(PERIPHC_SPI3, CLOCK_TYPE_PCMT),
214 TYPE(PERIPHC_XIO, CLOCK_TYPE_PCMT),
215 TYPE(PERIPHC_I2C1, CLOCK_TYPE_PCMT),
216 TYPE(PERIPHC_DVC_I2C, CLOCK_TYPE_PCMT),
217 TYPE(PERIPHC_TWC, CLOCK_TYPE_PCMT),
218 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
219 TYPE(PERIPHC_SPI1, CLOCK_TYPE_PCMT),
220 TYPE(PERIPHC_DISP1, CLOCK_TYPE_PDCT),
221 TYPE(PERIPHC_DISP2, CLOCK_TYPE_PDCT),
224 TYPE(PERIPHC_CVE, CLOCK_TYPE_PDCT),
225 TYPE(PERIPHC_IDE0, CLOCK_TYPE_PCMT),
226 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
227 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
228 TYPE(PERIPHC_SDMMC1, CLOCK_TYPE_PCMT),
229 TYPE(PERIPHC_SDMMC2, CLOCK_TYPE_PCMT),
230 TYPE(PERIPHC_G3D, CLOCK_TYPE_MCPA),
231 TYPE(PERIPHC_G2D, CLOCK_TYPE_MCPA),
234 TYPE(PERIPHC_NDFLASH, CLOCK_TYPE_PCMT),
235 TYPE(PERIPHC_SDMMC4, CLOCK_TYPE_PCMT),
236 TYPE(PERIPHC_VFIR, CLOCK_TYPE_PCMT),
237 TYPE(PERIPHC_EPP, CLOCK_TYPE_MCPA),
238 TYPE(PERIPHC_MPE, CLOCK_TYPE_MCPA),
239 TYPE(PERIPHC_MIPI, CLOCK_TYPE_PCMT),
240 TYPE(PERIPHC_UART1, CLOCK_TYPE_PCMT),
241 TYPE(PERIPHC_UART2, CLOCK_TYPE_PCMT),
244 TYPE(PERIPHC_HOST1X, CLOCK_TYPE_MCPA),
245 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
246 TYPE(PERIPHC_TVO, CLOCK_TYPE_PDCT),
247 TYPE(PERIPHC_HDMI, CLOCK_TYPE_PDCT),
248 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
249 TYPE(PERIPHC_TVDAC, CLOCK_TYPE_PDCT),
250 TYPE(PERIPHC_I2C2, CLOCK_TYPE_PCMT),
251 TYPE(PERIPHC_EMC, CLOCK_TYPE_MCPT),
254 TYPE(PERIPHC_UART3, CLOCK_TYPE_PCMT),
255 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
256 TYPE(PERIPHC_VI, CLOCK_TYPE_MCPA),
257 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
258 TYPE(PERIPHC_NONE, CLOCK_TYPE_NONE),
259 TYPE(PERIPHC_SPI4, CLOCK_TYPE_PCMT),
260 TYPE(PERIPHC_I2C3, CLOCK_TYPE_PCMT),
261 TYPE(PERIPHC_SDMMC3, CLOCK_TYPE_PCMT),
264 TYPE(PERIPHC_UART4, CLOCK_TYPE_PCMT),
265 TYPE(PERIPHC_UART5, CLOCK_TYPE_PCMT),
266 TYPE(PERIPHC_VDE, CLOCK_TYPE_PCMT),
267 TYPE(PERIPHC_OWR, CLOCK_TYPE_PCMT),
268 TYPE(PERIPHC_NOR, CLOCK_TYPE_PCMT),
269 TYPE(PERIPHC_CSITE, CLOCK_TYPE_PCMT),
273 * This array translates a periph_id to a periphc_internal_id
275 * Not present/matched up:
276 * uint vi_sensor; _VI_SENSOR_0, 0x1A8
277 * SPDIF - which is both 0x08 and 0x0c
280 #define NONE(name) (-1)
281 #define OFFSET(name, value) PERIPHC_ ## name
282 static s8 periph_id_to_internal_id[PERIPH_ID_COUNT] = {
291 PERIPHC_UART2, /* and vfir 0x68 */
296 NONE(SPDIF), /* 0x08 and 0x0c, unclear which to use */
323 /* Middle word: 63:32 */
335 NONE(SBC1), /* SBC1, 0x34, is this SPI1? */
345 PERIPHC_TVO, /* also CVE 0x40 */
363 /* Upper word 95:64 */
398 * Get the oscillator frequency, from the corresponding hardware configuration
401 enum clock_osc_freq clock_get_osc_freq(void)
403 struct clk_rst_ctlr *clkrst =
404 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
407 reg = readl(&clkrst->crc_osc_ctrl);
408 return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
411 /* Returns a pointer to the registers of the given pll */
412 static struct clk_pll *get_pll(enum clock_id clkid)
414 struct clk_rst_ctlr *clkrst =
415 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
417 assert(clock_id_isvalid(clkid));
418 return &clkrst->crc_pll[clkid];
421 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
422 u32 divp, u32 cpcon, u32 lfcon)
424 struct clk_pll *pll = get_pll(clkid);
428 * We cheat by treating all PLL (except PLLU) in the same fashion.
429 * This works only because:
430 * - same fields are always mapped at same offsets, except DCCON
431 * - DCCON is always 0, doesn't conflict
432 * - M,N, P of PLLP values are ignored for PLLP
434 data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
435 writel(data, &pll->pll_misc);
437 data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
438 (0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
440 if (clkid == CLOCK_ID_USB)
441 data |= divp << PLLU_VCO_FREQ_SHIFT;
443 data |= divp << PLL_DIVP_SHIFT;
444 writel(data, &pll->pll_base);
446 /* calculate the stable time */
447 return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
450 /* return 1 if a peripheral ID is in range and valid */
451 static int clock_periph_id_isvalid(enum periph_id id)
453 if (id < PERIPH_ID_FIRST || id >= PERIPH_ID_COUNT)
454 printf("Peripheral id %d out of range\n", id);
457 case PERIPH_ID_RESERVED1:
458 case PERIPH_ID_RESERVED2:
459 case PERIPH_ID_RESERVED30:
460 case PERIPH_ID_RESERVED35:
461 case PERIPH_ID_RESERVED56:
462 case PERIPH_ID_RESERVED74:
463 case PERIPH_ID_RESERVED76:
464 case PERIPH_ID_RESERVED77:
465 case PERIPH_ID_RESERVED78:
466 case PERIPH_ID_RESERVED79:
467 case PERIPH_ID_RESERVED80:
468 case PERIPH_ID_RESERVED81:
469 case PERIPH_ID_RESERVED82:
470 case PERIPH_ID_RESERVED83:
471 printf("Peripheral id %d is reserved\n", id);
480 /* Returns a pointer to the clock source register for a peripheral */
481 static u32 *get_periph_source_reg(enum periph_id periph_id)
483 struct clk_rst_ctlr *clkrst =
484 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
485 enum periphc_internal_id internal_id;
487 assert(clock_periph_id_isvalid(periph_id));
488 internal_id = periph_id_to_internal_id[periph_id];
489 assert(internal_id != -1);
490 return &clkrst->crc_clk_src[internal_id];
493 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
496 u32 *reg = get_periph_source_reg(periph_id);
501 value &= ~OUT_CLK_SOURCE_MASK;
502 value |= source << OUT_CLK_SOURCE_SHIFT;
504 value &= ~OUT_CLK_DIVISOR_MASK;
505 value |= divisor << OUT_CLK_DIVISOR_SHIFT;
510 void clock_ll_set_source(enum periph_id periph_id, unsigned source)
512 u32 *reg = get_periph_source_reg(periph_id);
514 clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
515 source << OUT_CLK_SOURCE_SHIFT);
519 * Given the parent's rate and the required rate for the children, this works
520 * out the peripheral clock divider to use, in 7.1 binary format.
522 * @param parent_rate clock rate of parent clock in Hz
523 * @param rate required clock rate for this clock
524 * @return divider which should be used
526 static int clk_div7_1_get_divider(unsigned long parent_rate,
529 u64 divider = parent_rate * 2;
532 do_div(divider, rate);
534 if ((s64)divider - 2 < 0)
537 if ((s64)divider - 2 > 255)
544 * Given the parent's rate and the divider in 7.1 format, this works out the
545 * resulting peripheral clock rate.
547 * @param parent_rate clock rate of parent clock in Hz
548 * @param divider which should be used in 7.1 format
549 * @return effective clock rate of peripheral
551 static unsigned long get_rate_from_divider(unsigned long parent_rate,
556 rate = (u64)parent_rate * 2;
557 do_div(rate, divider + 2);
561 unsigned long clock_get_periph_rate(enum periph_id periph_id,
562 enum clock_id parent)
564 u32 *reg = get_periph_source_reg(periph_id);
566 return get_rate_from_divider(pll_rate[parent],
567 (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
571 * Find the best available 7.1 format divisor given a parent clock rate and
572 * required child clock rate. This function assumes that a second-stage
573 * divisor is available which can divide by powers of 2 from 1 to 256.
575 * @param parent_rate clock rate of parent clock in Hz
576 * @param rate required clock rate for this clock
577 * @param extra_div value for the second-stage divisor (not set if this
578 * function returns -1.
579 * @return divider which should be used, or -1 if nothing is valid
582 static int find_best_divider(unsigned long parent_rate, unsigned long rate,
586 int best_divider = -1;
587 int best_error = rate;
589 /* try dividers from 1 to 256 and find closest match */
590 for (shift = 0; shift <= 8 && best_error > 0; shift++) {
591 unsigned divided_parent = parent_rate >> shift;
592 int divider = clk_div7_1_get_divider(divided_parent, rate);
593 unsigned effective_rate = get_rate_from_divider(divided_parent,
595 int error = rate - effective_rate;
597 /* Given a valid divider, look for the lowest error */
598 if (divider != -1 && error < best_error) {
600 *extra_div = 1 << shift;
601 best_divider = divider;
605 /* return what we found - *extra_div will already be set */
610 * Given a peripheral ID and the required source clock, this returns which
611 * value should be programmed into the source mux for that peripheral.
613 * There is special code here to handle the one source type with 5 sources.
615 * @param periph_id peripheral to start
616 * @param source PLL id of required parent clock
617 * @param mux_bits Set to number of bits in mux register: 2 or 4
618 * @return mux value (0-4, or -1 if not found)
620 static int get_periph_clock_source(enum periph_id periph_id,
621 enum clock_id parent, int *mux_bits)
623 enum clock_type_id type;
624 enum periphc_internal_id internal_id;
627 assert(clock_periph_id_isvalid(periph_id));
629 internal_id = periph_id_to_internal_id[periph_id];
630 assert(periphc_internal_id_isvalid(internal_id));
632 type = clock_periph_type[internal_id];
633 assert(clock_type_id_isvalid(type));
635 /* Special case here for the clock with a 4-bit source mux */
636 if (type == CLOCK_TYPE_PCXTS)
641 for (mux = 0; mux < CLOCK_MAX_MUX; mux++)
642 if (clock_source[type][mux] == parent)
646 * Not found: it might be looking for the 'S' in CLOCK_TYPE_PCXTS
647 * which is not in our table. If not, then they are asking for a
648 * source which this peripheral can't access through its mux.
650 assert(type == CLOCK_TYPE_PCXTS);
651 assert(parent == CLOCK_ID_SFROM32KHZ);
652 if (type == CLOCK_TYPE_PCXTS && parent == CLOCK_ID_SFROM32KHZ)
653 return 4; /* mux value for this clock */
655 /* if we get here, either us or the caller has made a mistake */
656 printf("Caller requested bad clock: periph=%d, parent=%d\n", periph_id,
662 * Adjust peripheral PLL to use the given divider and source.
664 * @param periph_id peripheral to adjust
665 * @param parent Required parent clock (for source mux)
666 * @param divider Required divider in 7.1 format
667 * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
668 * for this peripheral)
670 static int adjust_periph_pll(enum periph_id periph_id,
671 enum clock_id parent, unsigned divider)
673 u32 *reg = get_periph_source_reg(periph_id);
677 clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
678 divider << OUT_CLK_DIVISOR_SHIFT);
681 /* work out the source clock and set it */
682 source = get_periph_clock_source(periph_id, parent, &mux_bits);
686 clrsetbits_le32(reg, OUT_CLK_SOURCE4_MASK,
687 source << OUT_CLK_SOURCE4_SHIFT);
689 clrsetbits_le32(reg, OUT_CLK_SOURCE_MASK,
690 source << OUT_CLK_SOURCE_SHIFT);
696 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
697 enum clock_id parent, unsigned rate, int *extra_div)
699 unsigned effective_rate;
703 divider = find_best_divider(pll_rate[parent], rate, extra_div);
705 divider = clk_div7_1_get_divider(pll_rate[parent], rate);
706 assert(divider >= 0);
707 if (adjust_periph_pll(periph_id, parent, divider))
709 debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
710 get_periph_source_reg(periph_id),
711 readl(get_periph_source_reg(periph_id)));
713 /* Check what we ended up with. This shouldn't matter though */
714 effective_rate = clock_get_periph_rate(periph_id, parent);
716 effective_rate /= *extra_div;
717 if (rate != effective_rate)
718 debug("Requested clock rate %u not honored (got %u)\n",
719 rate, effective_rate);
720 return effective_rate;
723 unsigned clock_start_periph_pll(enum periph_id periph_id,
724 enum clock_id parent, unsigned rate)
726 unsigned effective_rate;
728 reset_set_enable(periph_id, 1);
729 clock_enable(periph_id);
731 effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
734 reset_set_enable(periph_id, 0);
735 return effective_rate;
738 void clock_set_enable(enum periph_id periph_id, int enable)
740 struct clk_rst_ctlr *clkrst =
741 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
742 u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
745 /* Enable/disable the clock to this peripheral */
746 assert(clock_periph_id_isvalid(periph_id));
749 reg |= PERIPH_MASK(periph_id);
751 reg &= ~PERIPH_MASK(periph_id);
755 void clock_enable(enum periph_id clkid)
757 clock_set_enable(clkid, 1);
760 void clock_disable(enum periph_id clkid)
762 clock_set_enable(clkid, 0);
765 void reset_set_enable(enum periph_id periph_id, int enable)
767 struct clk_rst_ctlr *clkrst =
768 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
769 u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
772 /* Enable/disable reset to the peripheral */
773 assert(clock_periph_id_isvalid(periph_id));
776 reg |= PERIPH_MASK(periph_id);
778 reg &= ~PERIPH_MASK(periph_id);
782 void reset_periph(enum periph_id periph_id, int us_delay)
784 /* Put peripheral into reset */
785 reset_set_enable(periph_id, 1);
789 reset_set_enable(periph_id, 0);
794 void reset_cmplx_set_enable(int cpu, int which, int reset)
796 struct clk_rst_ctlr *clkrst =
797 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
800 /* Form the mask, which depends on the cpu chosen. Tegra2 has 2 */
801 assert(cpu >= 0 && cpu < 2);
804 /* either enable or disable those reset for that CPU */
806 writel(mask, &clkrst->crc_cpu_cmplx_set);
808 writel(mask, &clkrst->crc_cpu_cmplx_clr);
811 unsigned clock_get_rate(enum clock_id clkid)
819 parent_rate = osc_freq[clock_get_osc_freq()];
820 if (clkid == CLOCK_ID_OSC)
823 pll = get_pll(clkid);
824 base = readl(&pll->pll_base);
826 /* Oh for bf_unpack()... */
827 rate = parent_rate * ((base & PLL_DIVN_MASK) >> PLL_DIVN_SHIFT);
828 divm = (base & PLL_DIVM_MASK) >> PLL_DIVM_SHIFT;
829 if (clkid == CLOCK_ID_USB)
830 divm <<= (base & PLLU_VCO_FREQ_MASK) >> PLLU_VCO_FREQ_SHIFT;
832 divm <<= (base & PLL_DIVP_MASK) >> PLL_DIVP_SHIFT;
838 * Set the output frequency you want for each PLL clock.
839 * PLL output frequencies are programmed by setting their N, M and P values.
840 * The governing equations are:
841 * VCO = (Fi / m) * n, Fo = VCO / (2^p)
842 * where Fo is the output frequency from the PLL.
843 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
844 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
845 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
847 * @param n PLL feedback divider(DIVN)
848 * @param m PLL input divider(DIVN)
849 * @param p post divider(DIVP)
850 * @param cpcon base PLL charge pump(CPCON)
851 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
852 * be overriden), 1 if PLL is already correct
854 static int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
860 pll = get_pll(clkid);
862 base_reg = readl(&pll->pll_base);
864 /* Set BYPASS, m, n and p to PLL_BASE */
865 base_reg &= ~PLL_DIVM_MASK;
866 base_reg |= m << PLL_DIVM_SHIFT;
868 base_reg &= ~PLL_DIVN_MASK;
869 base_reg |= n << PLL_DIVN_SHIFT;
871 base_reg &= ~PLL_DIVP_MASK;
872 base_reg |= p << PLL_DIVP_SHIFT;
874 if (clkid == CLOCK_ID_PERIPH) {
876 * If the PLL is already set up, check that it is correct
877 * and record this info for clock_verify() to check.
879 if (base_reg & PLL_BASE_OVRRIDE_MASK) {
880 base_reg |= PLL_ENABLE_MASK;
881 if (base_reg != readl(&pll->pll_base))
883 return pllp_valid ? 1 : -1;
885 base_reg |= PLL_BASE_OVRRIDE_MASK;
888 base_reg |= PLL_BYPASS_MASK;
889 writel(base_reg, &pll->pll_base);
891 /* Set cpcon to PLL_MISC */
892 misc_reg = readl(&pll->pll_misc);
893 misc_reg &= ~PLL_CPCON_MASK;
894 misc_reg |= cpcon << PLL_CPCON_SHIFT;
895 writel(misc_reg, &pll->pll_misc);
898 base_reg |= PLL_ENABLE_MASK;
899 writel(base_reg, &pll->pll_base);
902 base_reg &= ~PLL_BYPASS_MASK;
903 writel(base_reg, &pll->pll_base);
908 void clock_ll_start_uart(enum periph_id periph_id)
910 /* Assert UART reset and enable clock */
911 reset_set_enable(periph_id, 1);
912 clock_enable(periph_id);
913 clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
918 /* De-assert reset to UART */
919 reset_set_enable(periph_id, 0);
922 #ifdef CONFIG_OF_CONTROL
924 * Convert a device tree clock ID to our peripheral ID. They are mostly
925 * the same but we are very cautious so we check that a valid clock ID is
928 * @param clk_id Clock ID according to tegra2 device tree binding
929 * @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
931 static enum periph_id clk_id_to_periph_id(int clk_id)
934 return PERIPH_ID_NONE;
957 return PERIPH_ID_NONE;
963 int clock_decode_periph_id(const void *blob, int node)
969 err = fdtdec_get_int_array(blob, node, "clocks", cell,
973 id = clk_id_to_periph_id(cell[1]);
974 assert(clock_periph_id_isvalid(id));
977 #endif /* CONFIG_OF_CONTROL */
979 int clock_verify(void)
981 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
982 u32 reg = readl(&pll->pll_base);
985 printf("Warning: PLLP %x is not correct\n", reg);
988 debug("PLLX %x is correct\n", reg);
992 void clock_early_init(void)
995 * PLLP output frequency set to 216MHz
996 * PLLC output frequency set to 600Mhz
998 * TODO: Can we calculate these values instead of hard-coding?
1000 switch (clock_get_osc_freq()) {
1001 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
1002 clock_set_rate(CLOCK_ID_PERIPH, 432, 12, 1, 8);
1003 clock_set_rate(CLOCK_ID_CGENERAL, 600, 12, 0, 8);
1006 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
1007 clock_set_rate(CLOCK_ID_PERIPH, 432, 26, 1, 8);
1008 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
1011 case CLOCK_OSC_FREQ_13_0:
1012 case CLOCK_OSC_FREQ_19_2:
1015 * These are not supported. It is too early to print a
1016 * message and the UART likely won't work anyway due to the
1017 * oscillator being wrong.
1023 void clock_init(void)
1025 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
1026 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
1027 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
1028 pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
1029 pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
1030 debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
1031 debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
1032 debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);