2 * Copyright (c) 2011 The Chromium OS Authors.
3 * See file CREDITS for list of people who contributed to this
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 /* Tegra2 Clock control functions */
25 #include <asm/arch/clk_rst.h>
26 #include <asm/arch/clock.h>
27 #include <asm/arch/timer.h>
28 #include <asm/arch/tegra2.h>
33 ({ if (!(x)) printf("Assertion failure '%s' %s line %d\n", \
34 #x, __FILE__, __LINE__); })
40 * Get the oscillator frequency, from the corresponding hardware configuration
43 enum clock_osc_freq clock_get_osc_freq(void)
45 struct clk_rst_ctlr *clkrst =
46 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
49 reg = readl(&clkrst->crc_osc_ctrl);
50 return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
53 unsigned long clock_start_pll(enum clock_pll_id clkid, u32 divm, u32 divn,
54 u32 divp, u32 cpcon, u32 lfcon)
56 struct clk_rst_ctlr *clkrst =
57 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
61 assert(clock_pll_id_isvalid(clkid));
62 pll = &clkrst->crc_pll[clkid];
65 * We cheat by treating all PLL (except PLLU) in the same fashion.
66 * This works only because:
67 * - same fields are always mapped at same offsets, except DCCON
68 * - DCCON is always 0, doesn't conflict
69 * - M,N, P of PLLP values are ignored for PLLP
71 data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
72 writel(data, &pll->pll_misc);
74 data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
75 (0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
77 if (clkid == CLOCK_PLL_ID_USB)
78 data |= divp << PLLU_VCO_FREQ_SHIFT;
80 data |= divp << PLL_DIVP_SHIFT;
81 writel(data, &pll->pll_base);
83 /* calculate the stable time */
84 return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
87 void clock_set_enable(enum periph_id periph_id, int enable)
89 struct clk_rst_ctlr *clkrst =
90 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
91 u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
94 /* Enable/disable the clock to this peripheral */
95 assert(clock_periph_id_isvalid(periph_id));
98 reg |= PERIPH_MASK(periph_id);
100 reg &= ~PERIPH_MASK(periph_id);
104 void clock_enable(enum periph_id clkid)
106 clock_set_enable(clkid, 1);
109 void clock_disable(enum periph_id clkid)
111 clock_set_enable(clkid, 0);
114 void reset_set_enable(enum periph_id periph_id, int enable)
116 struct clk_rst_ctlr *clkrst =
117 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
118 u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
121 /* Enable/disable reset to the peripheral */
122 assert(clock_periph_id_isvalid(periph_id));
125 reg |= PERIPH_MASK(periph_id);
127 reg &= ~PERIPH_MASK(periph_id);
131 void reset_periph(enum periph_id periph_id, int us_delay)
133 /* Put peripheral into reset */
134 reset_set_enable(periph_id, 1);
138 reset_set_enable(periph_id, 0);
143 void reset_cmplx_set_enable(int cpu, int which, int reset)
145 struct clk_rst_ctlr *clkrst =
146 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
149 /* Form the mask, which depends on the cpu chosen. Tegra2 has 2 */
150 assert(cpu >= 0 && cpu < 2);
153 /* either enable or disable those reset for that CPU */
155 writel(mask, &clkrst->crc_cpu_cmplx_set);
157 writel(mask, &clkrst->crc_cpu_cmplx_clr);