2 * (C) Copyright 2010-2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/tegra2.h>
27 #include <asm/arch/clk_rst.h>
28 #include <asm/arch/clock.h>
29 #include <asm/arch/pmc.h>
30 #include <asm/arch/pinmux.h>
31 #include <asm/arch/scu.h>
38 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
39 struct clk_pll *pll = &clkrst->crc_pll[CLOCK_ID_XCPU];
42 /* If PLLX is already enabled, just return */
43 if (readl(&pll->pll_base) & PLL_ENABLE_MASK)
47 writel(1 << PLL_CPCON_SHIFT, &pll->pll_misc);
49 /* Use 12MHz clock here */
50 reg = PLL_BYPASS_MASK | (12 << PLL_DIVM_SHIFT);
51 reg |= 1000 << PLL_DIVN_SHIFT;
52 writel(reg, &pll->pll_base);
54 reg |= PLL_ENABLE_MASK;
55 writel(reg, &pll->pll_base);
57 reg &= ~PLL_BYPASS_MASK;
58 writel(reg, &pll->pll_base);
61 static void enable_cpu_clock(int enable)
63 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
68 * Regardless of whether the request is to enable or disable the CPU
69 * clock, every processor in the CPU complex except the master (CPU 0)
70 * will have it's clock stopped because the AVP only talks to the
71 * master. The AVP does not know (nor does it need to know) that there
72 * are multiple processors in the CPU complex.
79 /* Wait until all clocks are stable */
80 udelay(PLL_STABILIZATION_DELAY);
82 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
83 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
87 * Read the register containing the individual CPU clock enables and
88 * always stop the clock to CPU 1.
90 clk = readl(&clkrst->crc_clk_cpu_cmplx);
91 clk |= 1 << CPU1_CLK_STP_SHIFT;
93 /* Stop/Unstop the CPU clock */
94 clk &= ~CPU0_CLK_STP_MASK;
95 clk |= !enable << CPU0_CLK_STP_SHIFT;
96 writel(clk, &clkrst->crc_clk_cpu_cmplx);
98 clock_enable(PERIPH_ID_CPU);
101 static int is_cpu_powered(void)
103 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
105 return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
108 static void remove_cpu_io_clamps(void)
110 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
113 /* Remove the clamps on the CPU I/O signals */
114 reg = readl(&pmc->pmc_remove_clamping);
116 writel(reg, &pmc->pmc_remove_clamping);
118 /* Give I/O signals time to stabilize */
119 udelay(IO_STABILIZATION_DELAY);
122 static void powerup_cpu(void)
124 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
126 int timeout = IO_STABILIZATION_DELAY;
128 if (!is_cpu_powered()) {
129 /* Toggle the CPU power state (OFF -> ON) */
130 reg = readl(&pmc->pmc_pwrgate_toggle);
133 writel(reg, &pmc->pmc_pwrgate_toggle);
135 /* Wait for the power to come up */
136 while (!is_cpu_powered()) {
138 printf("CPU failed to power up!\n");
144 * Remove the I/O clamps from CPU power partition.
145 * Recommended only on a Warm boot, if the CPU partition gets
146 * power gated. Shouldn't cause any harm when called after a
147 * cold boot according to HW, probably just redundant.
149 remove_cpu_io_clamps();
153 static void enable_cpu_power_rail(void)
155 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
158 reg = readl(&pmc->pmc_cntrl);
160 writel(reg, &pmc->pmc_cntrl);
163 * The TI PMU65861C needs a 3.75ms delay between enabling
164 * the power rail and enabling the CPU clock. This delay
165 * between SM1EN and SM1 is for switching time + the ramp
166 * up of the voltage to the CPU (VDD_CPU from PMU).
171 static void reset_A9_cpu(int reset)
174 * NOTE: Regardless of whether the request is to hold the CPU in reset
175 * or take it out of reset, every processor in the CPU complex
176 * except the master (CPU 0) will be held in reset because the
177 * AVP only talks to the master. The AVP does not know that there
178 * are multiple processors in the CPU complex.
181 /* Hold CPU 1 in reset, and CPU 0 if asked */
182 reset_cmplx_set_enable(1, crc_rst_cpu | crc_rst_de | crc_rst_debug, 1);
183 reset_cmplx_set_enable(0, crc_rst_cpu | crc_rst_de | crc_rst_debug,
186 /* Enable/Disable master CPU reset */
187 reset_set_enable(PERIPH_ID_CPU, reset);
190 static void clock_enable_coresight(int enable)
194 clock_set_enable(PERIPH_ID_CORESIGHT, enable);
195 reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
199 * Put CoreSight on PLLP_OUT0 (216 MHz) and divide it down by
200 * 1.5, giving an effective frequency of 144MHz.
201 * Set PLLP_OUT0 [bits31:30 = 00], and use a 7.1 divisor
202 * (bits 7:0), so 00000001b == 1.5 (n+1 + .5)
204 src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000);
205 clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
207 /* Unlock the CPU CoreSight interfaces */
209 writel(rst, CSITE_CPU_DBG0_LAR);
210 writel(rst, CSITE_CPU_DBG1_LAR);
214 void start_cpu(u32 reset_vector)
217 enable_cpu_power_rail();
219 /* Hold the CPUs in reset */
222 /* Disable the CPU clock */
225 /* Enable CoreSight */
226 clock_enable_coresight(1);
229 * Set the entry point for CPU execution from reset,
230 * if it's a non-zero value.
233 writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
235 /* Enable the CPU clock */
238 /* If the CPU doesn't already have power, power it up */
241 /* Take the CPU out of reset */
249 writel((HALT_COP_EVENT_JTAG | HALT_COP_EVENT_IRQ_1 \
250 | HALT_COP_EVENT_FIQ_1 | (FLOW_MODE_STOP<<29)),
251 FLOW_CTLR_HALT_COP_EVENTS);
255 void enable_scu(void)
257 struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
260 /* If SCU already setup/enabled, return */
261 if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
264 /* Invalidate all ways for all processors */
265 writel(0xFFFF, &scu->scu_inv_all);
267 /* Enable SCU - bit 0 */
268 reg = readl(&scu->scu_ctrl);
269 reg |= SCU_CTRL_ENABLE;
270 writel(reg, &scu->scu_ctrl);
273 void init_pmc_scratch(void)
275 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
278 /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
279 for (i = 0; i < 23; i++)
280 writel(0, &pmc->pmc_scratch1+i);
282 /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
283 writel(CONFIG_SYS_BOARD_ODMDATA, &pmc->pmc_scratch20);
288 struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
291 writel(0xC0, &pmt->pmt_cfg_ctl);
295 * Need to set this before cold-booting,
296 * otherwise we'll end up in an infinite loop.
306 /* Init Debug UART Port (115200 8n1) */
309 /* Init PMC scratch memory */
313 #ifdef CONFIG_ENABLE_CORTEXA9
314 /* take the mpcore out of reset */
317 /* configure cache */