2 * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
4 * Based on allwinner u-boot sources rsb code which is:
5 * (C) Copyright 2007-2013
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * lixiang <lixiang@allwinnertech.com>
9 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/gpio.h>
16 #include <asm/arch/prcm.h>
17 #include <asm/arch/rsb.h>
19 static void rsb_cfg_io(void)
21 #ifdef CONFIG_MACH_SUN8I
22 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL0_R_RSB_SCK);
23 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL1_R_RSB_SDA);
24 sunxi_gpio_set_pull(SUNXI_GPL(0), 1);
25 sunxi_gpio_set_pull(SUNXI_GPL(1), 1);
26 sunxi_gpio_set_drv(SUNXI_GPL(0), 2);
27 sunxi_gpio_set_drv(SUNXI_GPL(1), 2);
28 #elif defined CONFIG_MACH_SUN9I
29 sunxi_gpio_set_cfgpin(SUNXI_GPN(0), SUN9I_GPN0_R_RSB_SCK);
30 sunxi_gpio_set_cfgpin(SUNXI_GPN(1), SUN9I_GPN1_R_RSB_SDA);
31 sunxi_gpio_set_pull(SUNXI_GPN(0), 1);
32 sunxi_gpio_set_pull(SUNXI_GPN(1), 1);
33 sunxi_gpio_set_drv(SUNXI_GPN(0), 2);
34 sunxi_gpio_set_drv(SUNXI_GPN(1), 2);
36 #error unsupported MACH_SUNXI
40 static void rsb_set_clk(void)
42 struct sunxi_rsb_reg * const rsb =
43 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
47 /* Source is Hosc24M, set RSB clk to 3Mhz */
48 div = 24000000 / 3000000 / 2 - 1;
53 writel((cd_odly << 8) | div, &rsb->ccr);
58 struct sunxi_rsb_reg * const rsb =
59 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
63 /* Enable RSB and PIO clk, and de-assert their resets */
64 prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB);
66 writel(RSB_CTRL_SOFT_RST, &rsb->ctrl);
70 static int rsb_await_trans(void)
72 struct sunxi_rsb_reg * const rsb =
73 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
74 unsigned long tmo = timer_get_us() + 1000000;
79 stat = readl(&rsb->stat);
80 if (stat & RSB_STAT_LBSY_INT) {
84 if (stat & RSB_STAT_TERR_INT) {
88 if (stat & RSB_STAT_TOVER_INT) {
92 if (timer_get_us() > tmo) {
97 writel(stat, &rsb->stat); /* Clear status bits */
102 int rsb_set_device_mode(u32 device_mode_data)
104 struct sunxi_rsb_reg * const rsb =
105 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
106 unsigned long tmo = timer_get_us() + 1000000;
108 writel(RSB_DMCR_DEVICE_MODE_START | device_mode_data, &rsb->dmcr);
110 while (readl(&rsb->dmcr) & RSB_DMCR_DEVICE_MODE_START) {
111 if (timer_get_us() > tmo)
115 return rsb_await_trans();
118 static int rsb_do_trans(void)
120 struct sunxi_rsb_reg * const rsb =
121 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
123 setbits_le32(&rsb->ctrl, RSB_CTRL_START_TRANS);
124 return rsb_await_trans();
127 int rsb_set_device_address(u16 device_addr, u16 runtime_addr)
129 struct sunxi_rsb_reg * const rsb =
130 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
132 writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_addr) |
133 RSB_DEVADDR_DEVICE_ADDR(device_addr), &rsb->devaddr);
134 writel(RSB_CMD_SET_RTSADDR, &rsb->cmd);
136 return rsb_do_trans();
139 int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data)
141 struct sunxi_rsb_reg * const rsb =
142 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
144 writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr);
145 writel(reg_addr, &rsb->addr);
146 writel(data, &rsb->data);
147 writel(RSB_CMD_BYTE_WRITE, &rsb->cmd);
149 return rsb_do_trans();
152 int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data)
154 struct sunxi_rsb_reg * const rsb =
155 (struct sunxi_rsb_reg *)SUNXI_RSB_BASE;
158 writel(RSB_DEVADDR_RUNTIME_ADDR(runtime_device_addr), &rsb->devaddr);
159 writel(reg_addr, &rsb->addr);
160 writel(RSB_CMD_BYTE_READ, &rsb->cmd);
162 ret = rsb_do_trans();
166 *data = readl(&rsb->data) & 0xff;