2 * Copyright (C) 2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * Based on code by Carl van Schaik <carl@ok-labs.com>.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <asm/macro.h>
24 #include <asm/arch/cpu.h>
29 * SECURE_RAM to text_end :
30 * ._secure_text section
31 * text_end to ALIGN_PAGE(text_end):
33 * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
34 * 1kB of stack per CPU (4 CPUs max).
37 .pushsection ._secure.text, "ax"
41 #define ONE_MS (CONFIG_TIMER_CLK_FREQ / 1000)
42 #define TEN_MS (10 * ONE_MS)
43 #define GICD_BASE 0x1c81000
44 #define GICC_BASE 0x1c82000
46 .macro timer_wait reg, ticks
48 movw \reg, #(\ticks & 0xffff)
49 movt \reg, #(\ticks >> 16)
50 mcr p15, 0, \reg, c14, c2, 0
52 @ Enable physical timer, mask interrupt
54 mcr p15, 0, \reg, c14, c2, 1
55 @ Poll physical timer until ISTATUS is on
57 mrc p15, 0, \reg, c14, c2, 1
62 mcr p15, 0, \reg, c14, c2, 1
71 mrc p15, 0, r7, c1, c1, 0
73 mcr p15, 0, r8, c1, c1, 0
76 @ Validate reason based on IAR and acknowledge
77 movw r8, #(GICC_BASE & 0xffff)
78 movt r8, #(GICC_BASE >> 16)
79 ldr r9, [r8, #GICC_IAR]
82 cmp r9, r10 @ skip spurious interrupt 1023
84 movw r10, #0x3fe @ ...and 1022
87 str r9, [r8, #GICC_EOIR] @ acknowledge the interrupt
94 movw r8, #(SUN7I_CPUCFG_BASE & 0xffff)
95 movt r8, #(SUN7I_CPUCFG_BASE >> 16)
97 @ Wait for the core to enter WFI
101 1: ldr r10, [r11, #0x48]
104 timer_wait r10, ONE_MS
109 str r10, [r11, #0x40]
113 lsl r9, r10, r9 @ r9 is now CPU mask
114 ldr r10, [r8, #0x1e4]
116 str r10, [r8, #0x1e4]
119 ldr r10, [r8, #0x1b4]
121 str r10, [r8, #0x1b4]
122 timer_wait r10, ONE_MS
124 @ Activate power clamp
126 1: str r10, [r8, #0x1b0]
132 @ Restore security level
133 out: mcr p15, 0, r7, c1, c1, 0
145 bl psci_get_cpu_stack_top @ get stack top of target CPU
146 str r2, [r0] @ store target PC at stack top
149 movw r0, #(SUN7I_CPUCFG_BASE & 0xffff)
150 movt r0, #(SUN7I_CPUCFG_BASE >> 16)
153 and r1, r1, #3 @ only care about first cluster
157 ldr r6, =psci_cpu_entry
158 str r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
160 @ Assert reset on target CPU
162 lsl r5, r1, #6 @ 64 bytes per CPU
163 add r5, r5, #0x40 @ Offset from base
164 add r5, r5, r0 @ CPU control block
165 str r6, [r5] @ Reset CPU
168 ldr r6, [r0, #0x184] @ CPUCFG_GEN_CTRL_REG
172 @ Lock CPU (Disable external debug access)
173 ldr r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
177 @ Release power clamp
181 str r6, [r0, #0x1b0] @ CPU1_PWR_CLAMP
184 timer_wait r1, TEN_MS
187 ldr r6, [r0, #0x1b4] @ CPU1_PWROFF_REG
191 @ Deassert reset on target CPU
195 @ Unlock CPU (Enable external debug access)
196 ldr r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
200 mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS
205 bl psci_cpu_off_common
207 @ Ask CPU0 to pull the rug...
208 movw r0, #(GICD_BASE & 0xffff)
209 movt r0, #(GICD_BASE >> 16)
211 movt r1, #1 @ Target is CPU0
212 str r1, [r0, #GICD_SGIR]
218 .globl psci_arch_init
222 movw r4, #(GICD_BASE & 0xffff)
223 movt r4, #(GICD_BASE >> 16)
225 ldr r5, [r4, #GICD_IGROUPRn]
226 bic r5, r5, #(1 << 15) @ SGI15 as Group-0
227 str r5, [r4, #GICD_IGROUPRn]
229 mov r5, #0 @ Set SGI15 priority to 0
230 strb r5, [r4, #(GICD_IPRIORITYRn + 15)]
232 add r4, r4, #0x1000 @ GICC address
235 str r5, [r4, #GICC_PMR] @ Be cool with non-secure
237 ldr r5, [r4, #GICC_CTLR]
238 orr r5, r5, #(1 << 3) @ Switch FIQEn on
239 str r5, [r4, #GICC_CTLR]
241 mrc p15, 0, r5, c1, c1, 0 @ Read SCR
242 orr r5, r5, #4 @ Enable FIQ in monitor mode
243 bic r5, r5, #1 @ Secure mode
244 mcr p15, 0, r5, c1, c1, 0 @ Write SCR
247 bl psci_get_cpu_id @ CPU ID => r0
248 bl psci_get_cpu_stack_top @ stack top => r0