2 * Copyright (C) 2015 - Chen-Yu Tsai
3 * Author: Chen-Yu Tsai <wens@csie.org>
5 * Based on psci_sun7i.S by Marc Zyngier <marc.zyngier@arm.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <asm/macro.h>
24 #include <asm/arch/cpu.h>
29 * SECURE_RAM to text_end :
30 * ._secure_text section
31 * text_end to ALIGN_PAGE(text_end):
33 * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
34 * 1kB of stack per CPU (4 CPUs max).
37 .pushsection ._secure.text, "ax"
41 #define ONE_MS (CONFIG_TIMER_CLK_FREQ / 1000)
42 #define TEN_MS (10 * ONE_MS)
43 #define GICD_BASE 0x1c81000
44 #define GICC_BASE 0x1c82000
46 .macro timer_wait reg, ticks
48 movw \reg, #(\ticks & 0xffff)
49 movt \reg, #(\ticks >> 16)
50 mcr p15, 0, \reg, c14, c2, 0
52 @ Enable physical timer, mask interrupt
54 mcr p15, 0, \reg, c14, c2, 1
55 @ Poll physical timer until ISTATUS is on
57 mrc p15, 0, \reg, c14, c2, 1
62 mcr p15, 0, \reg, c14, c2, 1
71 mrc p15, 0, r7, c1, c1, 0
73 mcr p15, 0, r8, c1, c1, 0
76 @ Validate reason based on IAR and acknowledge
77 movw r8, #(GICC_BASE & 0xffff)
78 movt r8, #(GICC_BASE >> 16)
79 ldr r9, [r8, #GICC_IAR]
82 cmp r9, r10 @ skip spurious interrupt 1023
84 movw r10, #0x3fe @ ...and 1022
87 str r9, [r8, #GICC_EOIR] @ acknowledge the interrupt
94 movw r8, #(SUN6I_CPUCFG_BASE & 0xffff)
95 movt r8, #(SUN6I_CPUCFG_BASE >> 16)
97 @ Wait for the core to enter WFI
101 1: ldr r10, [r11, #0x48]
104 timer_wait r10, ONE_MS
109 str r10, [r11, #0x40]
113 lsl r11, r10, r9 @ r11 is now CPU mask
114 ldr r10, [r8, #0x1e4]
116 str r10, [r8, #0x1e4]
118 movw r8, #(SUNXI_PRCM_BASE & 0xffff)
119 movt r8, #(SUNXI_PRCM_BASE >> 16)
122 ldr r10, [r8, #0x100]
124 str r10, [r8, #0x100]
125 timer_wait r10, ONE_MS
127 #ifdef CONFIG_MACH_SUN6I
128 @ Activate power clamp
132 str r10, [r12, #0x140]
135 movw r8, #(SUN6I_CPUCFG_BASE & 0xffff)
136 movt r8, #(SUN6I_CPUCFG_BASE >> 16)
139 ldr r10, [r8, #0x1e4]
141 str r10, [r8, #0x1e4]
143 @ Restore security level
144 out: mcr p15, 0, r7, c1, c1, 0
156 bl psci_get_cpu_stack_top @ get stack top of target CPU
157 str r2, [r0] @ store target PC at stack top
160 movw r0, #(SUN6I_CPUCFG_BASE & 0xffff)
161 movt r0, #(SUN6I_CPUCFG_BASE >> 16)
164 and r1, r1, #3 @ only care about first cluster
168 ldr r6, =psci_cpu_entry
169 str r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
171 @ Assert reset on target CPU
173 lsl r5, r1, #6 @ 64 bytes per CPU
174 add r5, r5, #0x40 @ Offset from base
175 add r5, r5, r0 @ CPU control block
176 str r6, [r5] @ Reset CPU
179 ldr r6, [r0, #0x184] @ CPUCFG_GEN_CTRL_REG
183 @ Lock CPU (Disable external debug access)
184 ldr r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
188 movw r0, #(SUNXI_PRCM_BASE & 0xffff)
189 movt r0, #(SUNXI_PRCM_BASE >> 16)
191 #ifdef CONFIG_MACH_SUN6I
192 @ Release power clamp
193 lsl r5, r1, #2 @ 1 register per CPU
194 add r5, r5, r0 @ PRCM
198 str r6, [r5, #0x140] @ CPUx_PWR_CLAMP
202 timer_wait r6, TEN_MS
205 ldr r6, [r0, #0x100] @ CPU_PWROFF_GATING
209 @ re-calculate CPU control register address
210 movw r0, #(SUN6I_CPUCFG_BASE & 0xffff)
211 movt r0, #(SUN6I_CPUCFG_BASE >> 16)
213 @ Deassert reset on target CPU
215 lsl r5, r1, #6 @ 64 bytes per CPU
216 add r5, r5, #0x40 @ Offset from base
217 add r5, r5, r0 @ CPU control block
220 @ Unlock CPU (Enable external debug access)
221 ldr r6, [r0, #0x1e4] @ CPUCFG_DBG_CTL1_REG
225 mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS
230 bl psci_cpu_off_common
232 @ Ask CPU0 to pull the rug...
233 movw r0, #(GICD_BASE & 0xffff)
234 movt r0, #(GICD_BASE >> 16)
236 movt r1, #1 @ Target is CPU0
237 str r1, [r0, #GICD_SGIR]
243 .globl psci_arch_init
247 movw r4, #(GICD_BASE & 0xffff)
248 movt r4, #(GICD_BASE >> 16)
250 ldr r5, [r4, #GICD_IGROUPRn]
251 bic r5, r5, #(1 << 15) @ SGI15 as Group-0
252 str r5, [r4, #GICD_IGROUPRn]
254 mov r5, #0 @ Set SGI15 priority to 0
255 strb r5, [r4, #(GICD_IPRIORITYRn + 15)]
257 add r4, r4, #0x1000 @ GICC address
260 str r5, [r4, #GICC_PMR] @ Be cool with non-secure
262 ldr r5, [r4, #GICC_CTLR]
263 orr r5, r5, #(1 << 3) @ Switch FIQEn on
264 str r5, [r4, #GICC_CTLR]
266 mrc p15, 0, r5, c1, c1, 0 @ Read SCR
267 orr r5, r5, #4 @ Enable FIQ in monitor mode
268 bic r5, r5, #1 @ Secure mode
269 mcr p15, 0, r5, c1, c1, 0 @ Write SCR
272 bl psci_get_cpu_id @ CPU ID => r0
273 bl psci_get_cpu_stack_top @ stack top => r0