arch/arm/cpu/armv7/sunxi/dram_sun8i_a83t.c

   1 /*
   2  * Sun8i a33 platform dram controller init.
   3  *
   4  * (C) Copyright 2007-2015 Allwinner Technology Co.
   5  *                         Jerry Wang <wangflord@allwinnertech.com>
   6  * (C) Copyright 2015      Vishnu Patekar <vishnupatekar0510@gmail.com>
   7  * (C) Copyright 2015      Hans de Goede <hdegoede@redhat.com>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11 #include <common.h>
  12 #include <errno.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/dram.h>
  16 #include <asm/arch/prcm.h>
  17
  18 #define DRAM_CLK_MUL 2
  19 #define DRAM_CLK_DIV 1
  20
  21 struct dram_para {
  22         u8 cs1;
  23         u8 seq;
  24         u8 bank;
  25         u8 rank;
  26         u8 rows;
  27         u8 bus_width;
  28         u16 page_size;
  29 };
  30
  31 static void mctl_set_cr(struct dram_para *para)
  32 {
  33         struct sunxi_mctl_com_reg * const mctl_com =
  34                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
  35
  36         writel(MCTL_CR_CS1_CONTROL(para->cs1) | MCTL_CR_UNKNOWN |
  37                 MCTL_CR_CHANNEL(1) | MCTL_CR_DDR3 |
  38                 (para->seq ? MCTL_CR_SEQUENCE : 0) |
  39                 ((para->bus_width == 16) ? MCTL_CR_BUSW16 : MCTL_CR_BUSW8) |
  40                 MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
  41                 MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank),
  42                 &mctl_com->cr);
  43 }
  44
  45 static void auto_detect_dram_size(struct dram_para *para)
  46 {
  47         u8 orig_rank = para->rank;
  48         int rows, columns;
  49
  50         /* Row detect */
  51         para->page_size = 512;
  52         para->seq = 1;
  53         para->rows = 16;
  54         para->rank = 1;
  55         mctl_set_cr(para);
  56         for (rows = 11 ; rows < 16 ; rows++) {
  57                 if (mctl_mem_matches(1 << (rows + 9))) /* row-column */
  58                         break;
  59         }
  60
  61         /* Column (page size) detect */
  62         para->rows = 11;
  63         para->page_size = 8192;
  64         mctl_set_cr(para);
  65         for (columns = 9 ; columns < 13 ; columns++) {
  66                 if (mctl_mem_matches(1 << columns))
  67                         break;
  68         }
  69
  70         para->seq = 0;
  71         para->rank = orig_rank;
  72         para->rows = rows;
  73         para->page_size = 1 << columns;
  74         mctl_set_cr(para);
  75 }
  76
  77 static inline int ns_to_t(int nanoseconds)
  78 {
  79         const unsigned int ctrl_freq =
  80                 CONFIG_DRAM_CLK * DRAM_CLK_MUL / DRAM_CLK_DIV;
  81
  82         return (ctrl_freq * nanoseconds + 999) / 1000;
  83 }
  84
  85 static void auto_set_timing_para(struct dram_para *para)
  86 {
  87         struct sunxi_mctl_ctl_reg * const mctl_ctl =
  88                 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  89         u32 reg_val;
  90
  91         u8 tccd         = 2;
  92         u8 tfaw         = ns_to_t(50);
  93         u8 trrd         = max(ns_to_t(10), 4);
  94         u8 trcd         = ns_to_t(15);
  95         u8 trc          = ns_to_t(53);
  96         u8 txp          = max(ns_to_t(8), 3);
  97         u8 twtr         = max(ns_to_t(8), 4);
  98         u8 trtp         = max(ns_to_t(8), 4);
  99         u8 twr          = max(ns_to_t(15), 3);
 100         u8 trp          = ns_to_t(15);
 101         u8 tras         = ns_to_t(38);
 102
 103         u16 trefi       = ns_to_t(7800) / 32;
 104         u16 trfc        = ns_to_t(350);
 105
 106         /* Fixed timing parameters */
 107         u8 tmrw         = 0;
 108         u8 tmrd         = 4;
 109         u8 tmod         = 12;
 110         u8 tcke         = 3;
 111         u8 tcksrx       = 5;
 112         u8 tcksre       = 5;
 113         u8 tckesr       = 4;
 114         u8 trasmax      = 24;
 115         u8 tcl          = 6; /* CL 12 */
 116         u8 tcwl         = 4; /* CWL 8 */
 117         u8 t_rdata_en   = 4;
 118         u8 wr_latency   = 2;
 119
 120         u32 tdinit0     = (500 * CONFIG_DRAM_CLK) + 1;          /* 500us */
 121         u32 tdinit1     = (360 * CONFIG_DRAM_CLK) / 1000 + 1;   /* 360ns */
 122         u32 tdinit2     = (200 * CONFIG_DRAM_CLK) + 1;          /* 200us */
 123         u32 tdinit3     = (1 * CONFIG_DRAM_CLK) + 1;            /* 1us */
 124
 125         u8 twtp         = tcwl + 2 + twr;       /* WL + BL / 2 + tWR */
 126         u8 twr2rd       = tcwl + 2 + twtr;      /* WL + BL / 2 + tWTR */
 127         u8 trd2wr       = tcl + 2 + 1 - tcwl;   /* RL + BL / 2 + 2 - WL */
 128
 129         /* Set work mode register */
 130         mctl_set_cr(para);
 131         /* Set mode register */
 132         writel(MCTL_MR0, &mctl_ctl->mr0);
 133         writel(MCTL_MR1, &mctl_ctl->mr1);
 134         writel(MCTL_MR2, &mctl_ctl->mr2);
 135         writel(MCTL_MR3, &mctl_ctl->mr3);
 136         /* Set dram timing */
 137         reg_val = (twtp << 24) | (tfaw << 16) | (trasmax << 8) | (tras << 0);
 138         writel(reg_val, &mctl_ctl->dramtmg0);
 139         reg_val = (txp << 16) | (trtp << 8) | (trc << 0);
 140         writel(reg_val, &mctl_ctl->dramtmg1);
 141         reg_val = (tcwl << 24) | (tcl << 16) | (trd2wr << 8) | (twr2rd << 0);
 142         writel(reg_val, &mctl_ctl->dramtmg2);
 143         reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0);
 144         writel(reg_val, &mctl_ctl->dramtmg3);
 145         reg_val = (trcd << 24) | (tccd << 16) | (trrd << 8) | (trp << 0);
 146         writel(reg_val, &mctl_ctl->dramtmg4);
 147         reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0);
 148         writel(reg_val, &mctl_ctl->dramtmg5);
 149         /* Set two rank timing and exit self-refresh timing */
 150         reg_val = readl(&mctl_ctl->dramtmg8);
 151         reg_val &= ~(0xff << 8);
 152         reg_val &= ~(0xff << 0);
 153         reg_val |= (0x33 << 8);
 154         reg_val |= (0x8 << 0);
 155         writel(reg_val, &mctl_ctl->dramtmg8);
 156         /* Set phy interface time */
 157         reg_val = (0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8)
 158                         | (wr_latency << 0);
 159         /* PHY interface write latency and read latency configure */
 160         writel(reg_val, &mctl_ctl->pitmg0);
 161         /* Set phy time  PTR0-2 use default */
 162         writel(((tdinit0 << 0) | (tdinit1 << 20)), &mctl_ctl->ptr3);
 163         writel(((tdinit2 << 0) | (tdinit3 << 20)), &mctl_ctl->ptr4);
 164         /* Set refresh timing */
 165         reg_val = (trefi << 16) | (trfc << 0);
 166         writel(reg_val, &mctl_ctl->rfshtmg);
 167 }
 168
 169 static void mctl_set_pir(u32 val)
 170 {
 171         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 172                 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 173
 174         writel(val, &mctl_ctl->pir);
 175         mctl_await_completion(&mctl_ctl->pgsr0, 0x1, 0x1);
 176 }
 177
 178 static void mctl_data_train_cfg(struct dram_para *para)
 179 {
 180         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 181                 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 182
 183         if (para->rank == 2)
 184                 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24);
 185         else
 186                 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24);
 187 }
 188
 189 static int mctl_train_dram(struct dram_para *para)
 190 {
 191         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 192                 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 193
 194         mctl_data_train_cfg(para);
 195         mctl_set_pir(0x5f3);
 196
 197         return ((readl(&mctl_ctl->pgsr0) >> 20) & 0xff) ? -EIO : 0;
 198 }
 199
 200 static void set_master_priority(void)
 201 {
 202         writel(0x00a0000d, MCTL_MASTER_CFG0(0));
 203         writel(0x00500064, MCTL_MASTER_CFG1(0));
 204         writel(0x07000009, MCTL_MASTER_CFG0(1));
 205         writel(0x00000600, MCTL_MASTER_CFG1(1));
 206         writel(0x01000009, MCTL_MASTER_CFG0(3));
 207         writel(0x00000064, MCTL_MASTER_CFG1(3));
 208         writel(0x08000009, MCTL_MASTER_CFG0(4));
 209         writel(0x00000640, MCTL_MASTER_CFG1(4));
 210         writel(0x20000308, MCTL_MASTER_CFG0(8));
 211         writel(0x00001000, MCTL_MASTER_CFG1(8));
 212         writel(0x02800009, MCTL_MASTER_CFG0(9));
 213         writel(0x00000100, MCTL_MASTER_CFG1(9));
 214         writel(0x01800009, MCTL_MASTER_CFG0(5));
 215         writel(0x00000100, MCTL_MASTER_CFG1(5));
 216         writel(0x01800009, MCTL_MASTER_CFG0(7));
 217         writel(0x00000100, MCTL_MASTER_CFG1(7));
 218         writel(0x00640009, MCTL_MASTER_CFG0(6));
 219         writel(0x00000032, MCTL_MASTER_CFG1(6));
 220         writel(0x0100000d, MCTL_MASTER_CFG0(2));
 221         writel(0x00500080, MCTL_MASTER_CFG1(2));
 222 }
 223
 224 static int mctl_channel_init(struct dram_para *para)
 225 {
 226         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 227                 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 228         struct sunxi_mctl_com_reg * const mctl_com =
 229                 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 230         u32 low_data_lines_status;  /* Training status of datalines 0 - 7 */
 231         u32 high_data_lines_status; /* Training status of datalines 8 - 15 */
 232         u32 i, rval;
 233
 234         auto_set_timing_para(para);
 235
 236         /* Set dram master access priority */
 237         writel(0x000101a0, &mctl_com->bwcr);
 238         /* set cpu high priority */
 239         writel(0x1, &mctl_com->mapr);
 240         set_master_priority();
 241         udelay(250);
 242
 243         /* Disable dram VTC */
 244         clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0 | 0x1 << 30);
 245         clrsetbits_le32(&mctl_ctl->pgcr1, 0x1 << 24, 0x1 << 26);
 246
 247         writel(0x94be6fa3, MCTL_PROTECT);
 248         udelay(100);
 249         clrsetbits_le32(MX_UPD2, 0xfff << 16, 0x50 << 26);
 250         writel(0x0, MCTL_PROTECT);
 251         udelay(100);
 252
 253
 254         /* Set ODT */
 255         if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
 256                 rval = 0x0;
 257         else
 258                 rval = 0x2;
 259
 260         for (i = 0 ; i < 11 ; i++) {
 261                 clrsetbits_le32(DATX0IOCR(i), (0x3 << 24) | (0x3 << 16),
 262                                 rval << 24);
 263                 clrsetbits_le32(DATX1IOCR(i), (0x3 << 24) | (0x3 << 16),
 264                                 rval << 24);
 265                 clrsetbits_le32(DATX2IOCR(i), (0x3 << 24) | (0x3 << 16),
 266                                 rval << 24);
 267                 clrsetbits_le32(DATX3IOCR(i), (0x3 << 24) | (0x3 << 16),
 268                                 rval << 24);
 269         }
 270
 271         for (i = 0; i < 31; i++)
 272                 clrsetbits_le32(CAIOCR(i), 0x3 << 26 | 0x3 << 16, 0x2 << 26);
 273
 274         /* set PLL configuration */
 275         if (CONFIG_DRAM_CLK >= 480)
 276                 setbits_le32(&mctl_ctl->pllgcr, 0x1 << 19);
 277         else
 278                 setbits_le32(&mctl_ctl->pllgcr, 0x3 << 19);
 279
 280         /* Auto detect dram config, set 2 rank and 16bit bus-width */
 281         para->cs1 = 0;
 282         para->rank = 2;
 283         para->bus_width = 16;
 284         mctl_set_cr(para);
 285
 286         /* Open DQS gating */
 287         clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6));
 288         clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7));
 289
 290         if (readl(&mctl_com->cr) & 0x1)
 291                 writel(0x00000303, &mctl_ctl->odtmap);
 292         else
 293                 writel(0x00000201, &mctl_ctl->odtmap);
 294
 295         mctl_data_train_cfg(para);
 296         /* ZQ calibration */
 297         clrsetbits_le32(ZQnPR(0), 0x000000ff, CONFIG_DRAM_ZQ & 0xff);
 298         clrsetbits_le32(ZQnPR(1), 0x000000ff, (CONFIG_DRAM_ZQ >> 8) & 0xff);
 299         /* CA calibration */
 300         mctl_set_pir(0x0201f3 | 0x1<<10);
 301
 302         /* DQS gate training */
 303         if (mctl_train_dram(para) != 0) {
 304                 low_data_lines_status  = (readl(DXnGSR0(0)) >> 24) & 0x03;
 305                 high_data_lines_status = (readl(DXnGSR0(1)) >> 24) & 0x03;
 306
 307                 if (low_data_lines_status == 0x3)
 308                         return -EIO;
 309
 310                 /* DRAM has only one rank */
 311                 para->rank = 1;
 312                 mctl_set_cr(para);
 313
 314                 if (low_data_lines_status == high_data_lines_status)
 315                         goto done; /* 16 bit bus, 1 rank */
 316
 317                 if (!(low_data_lines_status & high_data_lines_status)) {
 318                         /* Retry 16 bit bus-width with CS1 set */
 319                         para->cs1 = 1;
 320                         mctl_set_cr(para);
 321                         if (mctl_train_dram(para) == 0)
 322                                 goto done;
 323                 }
 324
 325                 /* Try 8 bit bus-width */
 326                 writel(0x0, DXnGCR0(1)); /* Disable high DQ */
 327                 para->cs1 = 0;
 328                 para->bus_width = 8;
 329                 mctl_set_cr(para);
 330                 if (mctl_train_dram(para) != 0)
 331                         return -EIO;
 332         }
 333 done:
 334         /* Check the dramc status */
 335         mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
 336
 337         /* Close DQS gating */
 338         setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6);
 339
 340         /* set PGCR3,CKE polarity */
 341         writel(0x00aa0060, &mctl_ctl->pgcr3);
 342         /* Enable master access */
 343         writel(0xffffffff, &mctl_com->maer);
 344
 345         return 0;
 346 }
 347
 348 static void mctl_sys_init(struct dram_para *para)
 349 {
 350         struct sunxi_ccm_reg * const ccm =
 351                         (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 352         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 353                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 354
 355         clrbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
 356         clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
 357         clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
 358         clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
 359         clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
 360         clrbits_le32(&ccm->dram_clk_cfg, 0x01<<31);
 361
 362         clock_set_pll5(CONFIG_DRAM_CLK * 1000000 * DRAM_CLK_MUL);
 363
 364         clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV_MASK,
 365                         CCM_DRAMCLK_CFG_DIV(DRAM_CLK_DIV) |
 366                         CCM_DRAMCLK_CFG_RST | CCM_DRAMCLK_CFG_UPD);
 367         mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
 368
 369         setbits_le32(&ccm->ahb_reset0_cfg, 1 << 14);
 370         setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
 371         setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
 372         setbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
 373
 374         setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
 375         setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
 376         setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
 377         setbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE);
 378
 379         /* Set dram master access priority */
 380         writel(0x0000e00f, &mctl_ctl->clken);   /* normal */
 381
 382         udelay(250);
 383 }
 384
 385 unsigned long sunxi_dram_init(void)
 386 {
 387         struct sunxi_mctl_com_reg * const mctl_com =
 388                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 389         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 390                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 391
 392         struct dram_para para = {
 393                 .cs1 = 0,
 394                 .bank = 1,
 395                 .rank = 1,
 396                 .rows = 15,
 397                 .bus_width = 16,
 398                 .page_size = 2048,
 399         };
 400
 401         setbits_le32(SUNXI_PRCM_BASE + 0x1e0, 0x1 << 8);
 402
 403         writel(0, (SUNXI_PRCM_BASE + 0x1e8));
 404         udelay(10);
 405
 406         mctl_sys_init(&para);
 407
 408         if (mctl_channel_init(&para) != 0)
 409                 return 0;
 410
 411         auto_detect_dram_size(&para);
 412
 413         /* Enable master software clk */
 414         writel(readl(&mctl_com->swonr) | 0x3ffff, &mctl_com->swonr);
 415
 416         /* Set DRAM ODT MAP */
 417         if (para.rank == 2)
 418                 writel(0x00000303, &mctl_ctl->odtmap);
 419         else
 420                 writel(0x00000201, &mctl_ctl->odtmap);
 421
 422         return para.page_size * (para.bus_width / 8) *
 423                 (1 << (para.bank + para.rank + para.rows));
 424 }