2 * Sun6i platform dram controller init.
4 * (C) Copyright 2007-2012
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Berg Xing <bergxing@allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
9 * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/clock.h>
17 #include <asm/arch/dram.h>
18 #include <asm/arch/prcm.h>
20 /* DRAM clk & zq defaults, maybe turn these into Kconfig options ? */
21 #define DRAM_CLK_DEFAULT 312000000
22 #define DRAM_ZQ_DEFAULT 0x78
24 struct dram_sun6i_para {
33 * Wait up to 1s for value to be set in given part of reg.
35 static void await_completion(u32 *reg, u32 mask, u32 val)
37 unsigned long tmo = timer_get_us() + 1000000;
39 while ((readl(reg) & mask) != val) {
40 if (timer_get_us() > tmo)
41 panic("Timeout initialising DRAM\n");
45 static void mctl_sys_init(void)
47 struct sunxi_ccm_reg * const ccm =
48 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
49 const int dram_clk_div = 2;
51 clock_set_pll5(DRAM_CLK_DEFAULT * dram_clk_div);
53 clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK,
54 CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST |
56 await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
58 writel(MDFS_CLK_DEFAULT, &ccm->mdfs_clk_cfg);
60 /* deassert mctl reset */
61 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
63 /* enable mctl clock */
64 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
67 static void mctl_dll_init(int ch_index, struct dram_sun6i_para *para)
69 struct sunxi_mctl_phy_reg *mctl_phy;
72 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
74 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
76 /* disable + reset dlls */
77 writel(MCTL_DLLCR_DISABLE, &mctl_phy->acdllcr);
78 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx0dllcr);
79 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx1dllcr);
80 if (para->bus_width == 32) {
81 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx2dllcr);
82 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx3dllcr);
86 /* enable + reset dlls */
87 writel(0, &mctl_phy->acdllcr);
88 writel(0, &mctl_phy->dx0dllcr);
89 writel(0, &mctl_phy->dx1dllcr);
90 if (para->bus_width == 32) {
91 writel(0, &mctl_phy->dx2dllcr);
92 writel(0, &mctl_phy->dx3dllcr);
96 /* enable and release reset of dlls */
97 writel(MCTL_DLLCR_NRESET, &mctl_phy->acdllcr);
98 writel(MCTL_DLLCR_NRESET, &mctl_phy->dx0dllcr);
99 writel(MCTL_DLLCR_NRESET, &mctl_phy->dx1dllcr);
100 if (para->bus_width == 32) {
101 writel(MCTL_DLLCR_NRESET, &mctl_phy->dx2dllcr);
102 writel(MCTL_DLLCR_NRESET, &mctl_phy->dx3dllcr);
107 static bool mctl_rank_detect(u32 *gsr0, int rank)
109 const u32 done = MCTL_DX_GSR0_RANK0_TRAIN_DONE << rank;
110 const u32 err = MCTL_DX_GSR0_RANK0_TRAIN_ERR << rank;
112 await_completion(gsr0, done, done);
113 await_completion(gsr0 + 0x10, done, done);
115 return !(readl(gsr0) & err) && !(readl(gsr0 + 0x10) & err);
118 static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para)
120 struct sunxi_mctl_com_reg * const mctl_com =
121 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
122 struct sunxi_mctl_ctl_reg *mctl_ctl;
123 struct sunxi_mctl_phy_reg *mctl_phy;
126 mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
127 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
129 mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL1_BASE;
130 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
133 writel(MCTL_MCMD_NOP, &mctl_ctl->mcmd);
134 await_completion(&mctl_ctl->mcmd, MCTL_MCMD_BUSY, 0);
136 /* PHY initialization */
137 writel(MCTL_PGCR, &mctl_phy->pgcr);
138 writel(MCTL_MR0, &mctl_phy->mr0);
139 writel(MCTL_MR1, &mctl_phy->mr1);
140 writel(MCTL_MR2, &mctl_phy->mr2);
141 writel(MCTL_MR3, &mctl_phy->mr3);
143 writel((MCTL_TITMSRST << 18) | (MCTL_TDLLLOCK << 6) | MCTL_TDLLSRST,
146 writel((MCTL_TDINIT1 << 19) | MCTL_TDINIT0, &mctl_phy->ptr1);
147 writel((MCTL_TDINIT3 << 17) | MCTL_TDINIT2, &mctl_phy->ptr2);
149 writel((MCTL_TCCD << 31) | (MCTL_TRC << 25) | (MCTL_TRRD << 21) |
150 (MCTL_TRAS << 16) | (MCTL_TRCD << 12) | (MCTL_TRP << 8) |
151 (MCTL_TWTR << 5) | (MCTL_TRTP << 2) | (MCTL_TMRD << 0),
154 writel((MCTL_TDQSCKMAX << 27) | (MCTL_TDQSCK << 24) |
155 (MCTL_TRFC << 16) | (MCTL_TRTODT << 11) |
156 ((MCTL_TMOD - 12) << 9) | (MCTL_TFAW << 3) | (0 << 2) |
157 (MCTL_TAOND << 0), &mctl_phy->dtpr1);
159 writel((MCTL_TDLLK << 19) | (MCTL_TCKE << 15) | (MCTL_TXPDLL << 10) |
160 (MCTL_TEXSR << 0), &mctl_phy->dtpr2);
162 writel(1, &mctl_ctl->dfitphyupdtype0);
163 writel(MCTL_DCR_DDR3, &mctl_phy->dcr);
164 writel(MCTL_DSGCR, &mctl_phy->dsgcr);
165 writel(MCTL_DXCCR, &mctl_phy->dxccr);
166 writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx0gcr);
167 writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx1gcr);
168 writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx2gcr);
169 writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx3gcr);
171 await_completion(&mctl_phy->pgsr, 0x03, 0x03);
173 writel(DRAM_ZQ_DEFAULT, &mctl_phy->zq0cr1);
175 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
176 writel(MCTL_PIR_STEP1, &mctl_phy->pir);
178 await_completion(&mctl_phy->pgsr, 0x1f, 0x1f);
181 if (!mctl_rank_detect(&mctl_phy->dx0gsr0, 1)) {
183 clrbits_le32(&mctl_phy->pgcr, MCTL_PGCR_RANK);
187 * channel detect, check channel 1 dx0 and dx1 have rank 0, if not
188 * assume nothing is connected to channel 1.
190 if (ch_index == 1 && !mctl_rank_detect(&mctl_phy->dx0gsr0, 0)) {
192 clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN);
196 /* bus width detect, if dx2 and dx3 don't have rank 0, assume 16 bit */
197 if (!mctl_rank_detect(&mctl_phy->dx2gsr0, 0)) {
198 para->bus_width = 16;
199 para->page_size = 2048;
200 setbits_le32(&mctl_phy->dx2dllcr, MCTL_DLLCR_DISABLE);
201 setbits_le32(&mctl_phy->dx3dllcr, MCTL_DLLCR_DISABLE);
202 clrbits_le32(&mctl_phy->dx2gcr, MCTL_DX_GCR_EN);
203 clrbits_le32(&mctl_phy->dx3gcr, MCTL_DX_GCR_EN);
206 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
207 writel(MCTL_PIR_STEP2, &mctl_phy->pir);
209 await_completion(&mctl_phy->pgsr, 0x11, 0x11);
211 if (readl(&mctl_phy->pgsr) & MCTL_PGSR_TRAIN_ERR_MASK)
212 panic("Training error initialising DRAM\n");
214 /* Move to configure state */
215 writel(MCTL_SCTL_CONFIG, &mctl_ctl->sctl);
216 await_completion(&mctl_ctl->sstat, 0x07, 0x01);
218 /* Set number of clks per micro-second */
219 writel(DRAM_CLK_DEFAULT / 1000000, &mctl_ctl->togcnt1u);
220 /* Set number of clks per 100 nano-seconds */
221 writel(DRAM_CLK_DEFAULT / 10000000, &mctl_ctl->togcnt100n);
222 /* Set memory timing registers */
223 writel(MCTL_TREFI, &mctl_ctl->trefi);
224 writel(MCTL_TMRD, &mctl_ctl->tmrd);
225 writel(MCTL_TRFC, &mctl_ctl->trfc);
226 writel((MCTL_TPREA << 16) | MCTL_TRP, &mctl_ctl->trp);
227 writel(MCTL_TRTW, &mctl_ctl->trtw);
228 writel(MCTL_TAL, &mctl_ctl->tal);
229 writel(MCTL_TCL, &mctl_ctl->tcl);
230 writel(MCTL_TCWL, &mctl_ctl->tcwl);
231 writel(MCTL_TRAS, &mctl_ctl->tras);
232 writel(MCTL_TRC, &mctl_ctl->trc);
233 writel(MCTL_TRCD, &mctl_ctl->trcd);
234 writel(MCTL_TRRD, &mctl_ctl->trrd);
235 writel(MCTL_TRTP, &mctl_ctl->trtp);
236 writel(MCTL_TWR, &mctl_ctl->twr);
237 writel(MCTL_TWTR, &mctl_ctl->twtr);
238 writel(MCTL_TEXSR, &mctl_ctl->texsr);
239 writel(MCTL_TXP, &mctl_ctl->txp);
240 writel(MCTL_TXPDLL, &mctl_ctl->txpdll);
241 writel(MCTL_TZQCS, &mctl_ctl->tzqcs);
242 writel(MCTL_TZQCSI, &mctl_ctl->tzqcsi);
243 writel(MCTL_TDQS, &mctl_ctl->tdqs);
244 writel(MCTL_TCKSRE, &mctl_ctl->tcksre);
245 writel(MCTL_TCKSRX, &mctl_ctl->tcksrx);
246 writel(MCTL_TCKE, &mctl_ctl->tcke);
247 writel(MCTL_TMOD, &mctl_ctl->tmod);
248 writel(MCTL_TRSTL, &mctl_ctl->trstl);
249 writel(MCTL_TZQCL, &mctl_ctl->tzqcl);
250 writel(MCTL_TMRR, &mctl_ctl->tmrr);
251 writel(MCTL_TCKESR, &mctl_ctl->tckesr);
252 writel(MCTL_TDPD, &mctl_ctl->tdpd);
254 /* Unknown magic performed by boot0 */
255 setbits_le32(&mctl_ctl->dfiodtcfg, 1 << 3);
256 clrbits_le32(&mctl_ctl->dfiodtcfg1, 0x1f);
258 /* Select 16/32-bits mode for MCTL */
259 if (para->bus_width == 16)
260 setbits_le32(&mctl_ctl->ppcfg, 1);
262 /* Set DFI timing registers */
263 writel(MCTL_TCWL, &mctl_ctl->dfitphywrl);
264 writel(MCTL_TCL - 1, &mctl_ctl->dfitrdden);
265 writel(MCTL_DFITPHYRDL, &mctl_ctl->dfitphyrdl);
266 writel(MCTL_DFISTCFG0, &mctl_ctl->dfistcfg0);
268 writel(MCTL_MCFG_DDR3, &mctl_ctl->mcfg);
270 /* DFI update configuration register */
271 writel(MCTL_DFIUPDCFG_UPD, &mctl_ctl->dfiupdcfg);
273 /* Move to access state */
274 writel(MCTL_SCTL_ACCESS, &mctl_ctl->sctl);
275 await_completion(&mctl_ctl->sstat, 0x07, 0x03);
278 static void mctl_com_init(struct dram_sun6i_para *para)
280 struct sunxi_mctl_com_reg * const mctl_com =
281 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
282 struct sunxi_mctl_phy_reg * const mctl_phy1 =
283 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
284 struct sunxi_prcm_reg * const prcm =
285 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
287 writel(MCTL_CR_UNKNOWN | MCTL_CR_CHANNEL(para->chan) | MCTL_CR_DDR3 |
288 ((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16) |
289 MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
290 MCTL_CR_BANK(1) | MCTL_CR_RANK(para->rank), &mctl_com->cr);
292 /* Unknown magic performed by boot0 */
293 setbits_le32(&mctl_com->dbgcr, (1 << 6));
295 if (para->chan == 1) {
296 /* Shutdown channel 1 */
297 setbits_le32(&mctl_phy1->aciocr, MCTL_ACIOCR_DISABLE);
298 setbits_le32(&mctl_phy1->dxccr, MCTL_DXCCR_DISABLE);
299 clrbits_le32(&mctl_phy1->dsgcr, MCTL_DSGCR_ENABLE);
301 * CH0 ?? this is what boot0 does. Leave as is until we can
304 setbits_le32(&prcm->vdd_sys_pwroff,
305 PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF);
309 static void mctl_port_cfg(void)
311 struct sunxi_mctl_com_reg * const mctl_com =
312 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
313 struct sunxi_ccm_reg * const ccm =
314 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
316 /* enable DRAM AXI clock for CPU access */
317 setbits_le32(&ccm->axi_gate, 1 << AXI_GATE_OFFSET_DRAM);
319 /* Bunch of magic writes performed by boot0 */
320 writel(0x00400302, &mctl_com->rmcr[0]);
321 writel(0x01000307, &mctl_com->rmcr[1]);
322 writel(0x00400302, &mctl_com->rmcr[2]);
323 writel(0x01000307, &mctl_com->rmcr[3]);
324 writel(0x01000307, &mctl_com->rmcr[4]);
325 writel(0x01000303, &mctl_com->rmcr[6]);
326 writel(0x01000303, &mctl_com->mmcr[0]);
327 writel(0x00400310, &mctl_com->mmcr[1]);
328 writel(0x01000307, &mctl_com->mmcr[2]);
329 writel(0x01000303, &mctl_com->mmcr[3]);
330 writel(0x01800303, &mctl_com->mmcr[4]);
331 writel(0x01800303, &mctl_com->mmcr[5]);
332 writel(0x01800303, &mctl_com->mmcr[6]);
333 writel(0x01800303, &mctl_com->mmcr[7]);
334 writel(0x01000303, &mctl_com->mmcr[8]);
335 writel(0x00000002, &mctl_com->mmcr[15]);
336 writel(0x00000310, &mctl_com->mbagcr[0]);
337 writel(0x00400310, &mctl_com->mbagcr[1]);
338 writel(0x00400310, &mctl_com->mbagcr[2]);
339 writel(0x00000307, &mctl_com->mbagcr[3]);
340 writel(0x00000317, &mctl_com->mbagcr[4]);
341 writel(0x00000307, &mctl_com->mbagcr[5]);
344 static bool mctl_mem_matches(u32 offset)
346 const int match_count = 64;
349 for (i = 0; i < match_count; i++) {
350 if (readl(CONFIG_SYS_SDRAM_BASE + i * 4) ==
351 readl(CONFIG_SYS_SDRAM_BASE + offset + i * 4))
355 return matches == match_count;
358 unsigned long sunxi_dram_init(void)
360 struct sunxi_mctl_com_reg * const mctl_com =
361 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
363 int bank, bus, columns;
365 /* Set initial parameters, these get modified by the autodetect code */
366 struct dram_sun6i_para para = {
376 mctl_dll_init(0, ¶);
377 mctl_dll_init(1, ¶);
379 setbits_le32(&mctl_com->ccr,
380 MCTL_CCR_MASTER_CLK_EN |
381 MCTL_CCR_CH0_CLK_EN |
382 MCTL_CCR_CH1_CLK_EN);
384 mctl_channel_init(0, ¶);
385 mctl_channel_init(1, ¶);
386 mctl_com_init(¶);
390 * Change to 1 ch / sequence / 8192 byte pages / 16 rows /
391 * 8 bit banks / 1 rank mode.
393 clrsetbits_le32(&mctl_com->cr,
394 MCTL_CR_CHANNEL_MASK | MCTL_CR_PAGE_SIZE_MASK |
395 MCTL_CR_ROW_MASK | MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK,
396 MCTL_CR_CHANNEL(1) | MCTL_CR_SEQUENCE |
397 MCTL_CR_PAGE_SIZE(8192) | MCTL_CR_ROW(16) |
398 MCTL_CR_BANK(1) | MCTL_CR_RANK(1));
400 /* Detect and set page size */
401 for (columns = 7; columns < 20; columns++) {
402 if (mctl_mem_matches(1 << columns))
405 bus = (para.bus_width == 32) ? 2 : 1;
407 para.page_size = (1 << columns) * (bus << 1);
408 clrsetbits_le32(&mctl_com->cr, MCTL_CR_PAGE_SIZE_MASK,
409 MCTL_CR_PAGE_SIZE(para.page_size));
411 /* Detect and set rows */
412 for (para.rows = 11; para.rows < 16; para.rows++) {
413 offset = 1 << (para.rows + columns + bus);
414 if (mctl_mem_matches(offset))
417 clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK,
418 MCTL_CR_ROW(para.rows));
420 /* Detect bank size */
421 offset = 1 << (para.rows + columns + bus + 2);
422 bank = mctl_mem_matches(offset) ? 0 : 1;
424 /* Restore interleave, chan and rank values, set bank size */
425 clrsetbits_le32(&mctl_com->cr,
426 MCTL_CR_CHANNEL_MASK | MCTL_CR_SEQUENCE |
427 MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK,
428 MCTL_CR_CHANNEL(para.chan) | MCTL_CR_BANK(bank) |
429 MCTL_CR_RANK(para.rank));
431 return 1 << (para.rank + para.rows + bank + columns + para.chan + bus);