2 * Sun6i platform dram controller init.
4 * (C) Copyright 2007-2012
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Berg Xing <bergxing@allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
9 * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/clock.h>
17 #include <asm/arch/dram.h>
18 #include <asm/arch/prcm.h>
20 #define DRAM_CLK (CONFIG_DRAM_CLK * 1000000)
22 struct dram_sun6i_para {
31 * Wait up to 1s for value to be set in given part of reg.
33 static void await_completion(u32 *reg, u32 mask, u32 val)
35 unsigned long tmo = timer_get_us() + 1000000;
37 while ((readl(reg) & mask) != val) {
38 if (timer_get_us() > tmo)
39 panic("Timeout initialising DRAM\n");
43 static void mctl_sys_init(void)
45 struct sunxi_ccm_reg * const ccm =
46 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
47 const int dram_clk_div = 2;
49 clock_set_pll5(DRAM_CLK * dram_clk_div, false);
51 clrsetbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK,
52 CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST |
54 await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
56 writel(MDFS_CLK_DEFAULT, &ccm->mdfs_clk_cfg);
58 /* deassert mctl reset */
59 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
61 /* enable mctl clock */
62 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
65 static void mctl_dll_init(int ch_index, struct dram_sun6i_para *para)
67 struct sunxi_mctl_phy_reg *mctl_phy;
70 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
72 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
74 /* disable + reset dlls */
75 writel(MCTL_DLLCR_DISABLE, &mctl_phy->acdllcr);
76 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx0dllcr);
77 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx1dllcr);
78 if (para->bus_width == 32) {
79 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx2dllcr);
80 writel(MCTL_DLLCR_DISABLE, &mctl_phy->dx3dllcr);
84 /* enable + reset dlls */
85 writel(0, &mctl_phy->acdllcr);
86 writel(0, &mctl_phy->dx0dllcr);
87 writel(0, &mctl_phy->dx1dllcr);
88 if (para->bus_width == 32) {
89 writel(0, &mctl_phy->dx2dllcr);
90 writel(0, &mctl_phy->dx3dllcr);
94 /* enable and release reset of dlls */
95 writel(MCTL_DLLCR_NRESET, &mctl_phy->acdllcr);
96 writel(MCTL_DLLCR_NRESET, &mctl_phy->dx0dllcr);
97 writel(MCTL_DLLCR_NRESET, &mctl_phy->dx1dllcr);
98 if (para->bus_width == 32) {
99 writel(MCTL_DLLCR_NRESET, &mctl_phy->dx2dllcr);
100 writel(MCTL_DLLCR_NRESET, &mctl_phy->dx3dllcr);
105 static bool mctl_rank_detect(u32 *gsr0, int rank)
107 const u32 done = MCTL_DX_GSR0_RANK0_TRAIN_DONE << rank;
108 const u32 err = MCTL_DX_GSR0_RANK0_TRAIN_ERR << rank;
110 await_completion(gsr0, done, done);
111 await_completion(gsr0 + 0x10, done, done);
113 return !(readl(gsr0) & err) && !(readl(gsr0 + 0x10) & err);
116 static void mctl_channel_init(int ch_index, struct dram_sun6i_para *para)
118 struct sunxi_mctl_com_reg * const mctl_com =
119 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
120 struct sunxi_mctl_ctl_reg *mctl_ctl;
121 struct sunxi_mctl_phy_reg *mctl_phy;
124 mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
125 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
127 mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL1_BASE;
128 mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
131 writel(MCTL_MCMD_NOP, &mctl_ctl->mcmd);
132 await_completion(&mctl_ctl->mcmd, MCTL_MCMD_BUSY, 0);
134 /* PHY initialization */
135 writel(MCTL_PGCR, &mctl_phy->pgcr);
136 writel(MCTL_MR0, &mctl_phy->mr0);
137 writel(MCTL_MR1, &mctl_phy->mr1);
138 writel(MCTL_MR2, &mctl_phy->mr2);
139 writel(MCTL_MR3, &mctl_phy->mr3);
141 writel((MCTL_TITMSRST << 18) | (MCTL_TDLLLOCK << 6) | MCTL_TDLLSRST,
144 writel((MCTL_TDINIT1 << 19) | MCTL_TDINIT0, &mctl_phy->ptr1);
145 writel((MCTL_TDINIT3 << 17) | MCTL_TDINIT2, &mctl_phy->ptr2);
147 writel((MCTL_TCCD << 31) | (MCTL_TRC << 25) | (MCTL_TRRD << 21) |
148 (MCTL_TRAS << 16) | (MCTL_TRCD << 12) | (MCTL_TRP << 8) |
149 (MCTL_TWTR << 5) | (MCTL_TRTP << 2) | (MCTL_TMRD << 0),
152 writel((MCTL_TDQSCKMAX << 27) | (MCTL_TDQSCK << 24) |
153 (MCTL_TRFC << 16) | (MCTL_TRTODT << 11) |
154 ((MCTL_TMOD - 12) << 9) | (MCTL_TFAW << 3) | (0 << 2) |
155 (MCTL_TAOND << 0), &mctl_phy->dtpr1);
157 writel((MCTL_TDLLK << 19) | (MCTL_TCKE << 15) | (MCTL_TXPDLL << 10) |
158 (MCTL_TEXSR << 0), &mctl_phy->dtpr2);
160 writel(1, &mctl_ctl->dfitphyupdtype0);
161 writel(MCTL_DCR_DDR3, &mctl_phy->dcr);
162 writel(MCTL_DSGCR, &mctl_phy->dsgcr);
163 writel(MCTL_DXCCR, &mctl_phy->dxccr);
164 writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx0gcr);
165 writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx1gcr);
166 writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx2gcr);
167 writel(MCTL_DX_GCR | MCTL_DX_GCR_EN, &mctl_phy->dx3gcr);
169 await_completion(&mctl_phy->pgsr, 0x03, 0x03);
171 writel(CONFIG_DRAM_ZQ, &mctl_phy->zq0cr1);
173 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
174 writel(MCTL_PIR_STEP1, &mctl_phy->pir);
176 await_completion(&mctl_phy->pgsr, 0x1f, 0x1f);
179 if (!mctl_rank_detect(&mctl_phy->dx0gsr0, 1)) {
181 clrbits_le32(&mctl_phy->pgcr, MCTL_PGCR_RANK);
185 * channel detect, check channel 1 dx0 and dx1 have rank 0, if not
186 * assume nothing is connected to channel 1.
188 if (ch_index == 1 && !mctl_rank_detect(&mctl_phy->dx0gsr0, 0)) {
190 clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN);
194 /* bus width detect, if dx2 and dx3 don't have rank 0, assume 16 bit */
195 if (!mctl_rank_detect(&mctl_phy->dx2gsr0, 0)) {
196 para->bus_width = 16;
197 para->page_size = 2048;
198 setbits_le32(&mctl_phy->dx2dllcr, MCTL_DLLCR_DISABLE);
199 setbits_le32(&mctl_phy->dx3dllcr, MCTL_DLLCR_DISABLE);
200 clrbits_le32(&mctl_phy->dx2gcr, MCTL_DX_GCR_EN);
201 clrbits_le32(&mctl_phy->dx3gcr, MCTL_DX_GCR_EN);
204 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS);
205 writel(MCTL_PIR_STEP2, &mctl_phy->pir);
207 await_completion(&mctl_phy->pgsr, 0x11, 0x11);
209 if (readl(&mctl_phy->pgsr) & MCTL_PGSR_TRAIN_ERR_MASK)
210 panic("Training error initialising DRAM\n");
212 /* Move to configure state */
213 writel(MCTL_SCTL_CONFIG, &mctl_ctl->sctl);
214 await_completion(&mctl_ctl->sstat, 0x07, 0x01);
216 /* Set number of clks per micro-second */
217 writel(DRAM_CLK / 1000000, &mctl_ctl->togcnt1u);
218 /* Set number of clks per 100 nano-seconds */
219 writel(DRAM_CLK / 10000000, &mctl_ctl->togcnt100n);
220 /* Set memory timing registers */
221 writel(MCTL_TREFI, &mctl_ctl->trefi);
222 writel(MCTL_TMRD, &mctl_ctl->tmrd);
223 writel(MCTL_TRFC, &mctl_ctl->trfc);
224 writel((MCTL_TPREA << 16) | MCTL_TRP, &mctl_ctl->trp);
225 writel(MCTL_TRTW, &mctl_ctl->trtw);
226 writel(MCTL_TAL, &mctl_ctl->tal);
227 writel(MCTL_TCL, &mctl_ctl->tcl);
228 writel(MCTL_TCWL, &mctl_ctl->tcwl);
229 writel(MCTL_TRAS, &mctl_ctl->tras);
230 writel(MCTL_TRC, &mctl_ctl->trc);
231 writel(MCTL_TRCD, &mctl_ctl->trcd);
232 writel(MCTL_TRRD, &mctl_ctl->trrd);
233 writel(MCTL_TRTP, &mctl_ctl->trtp);
234 writel(MCTL_TWR, &mctl_ctl->twr);
235 writel(MCTL_TWTR, &mctl_ctl->twtr);
236 writel(MCTL_TEXSR, &mctl_ctl->texsr);
237 writel(MCTL_TXP, &mctl_ctl->txp);
238 writel(MCTL_TXPDLL, &mctl_ctl->txpdll);
239 writel(MCTL_TZQCS, &mctl_ctl->tzqcs);
240 writel(MCTL_TZQCSI, &mctl_ctl->tzqcsi);
241 writel(MCTL_TDQS, &mctl_ctl->tdqs);
242 writel(MCTL_TCKSRE, &mctl_ctl->tcksre);
243 writel(MCTL_TCKSRX, &mctl_ctl->tcksrx);
244 writel(MCTL_TCKE, &mctl_ctl->tcke);
245 writel(MCTL_TMOD, &mctl_ctl->tmod);
246 writel(MCTL_TRSTL, &mctl_ctl->trstl);
247 writel(MCTL_TZQCL, &mctl_ctl->tzqcl);
248 writel(MCTL_TMRR, &mctl_ctl->tmrr);
249 writel(MCTL_TCKESR, &mctl_ctl->tckesr);
250 writel(MCTL_TDPD, &mctl_ctl->tdpd);
252 /* Unknown magic performed by boot0 */
253 setbits_le32(&mctl_ctl->dfiodtcfg, 1 << 3);
254 clrbits_le32(&mctl_ctl->dfiodtcfg1, 0x1f);
256 /* Select 16/32-bits mode for MCTL */
257 if (para->bus_width == 16)
258 setbits_le32(&mctl_ctl->ppcfg, 1);
260 /* Set DFI timing registers */
261 writel(MCTL_TCWL, &mctl_ctl->dfitphywrl);
262 writel(MCTL_TCL - 1, &mctl_ctl->dfitrdden);
263 writel(MCTL_DFITPHYRDL, &mctl_ctl->dfitphyrdl);
264 writel(MCTL_DFISTCFG0, &mctl_ctl->dfistcfg0);
266 writel(MCTL_MCFG_DDR3, &mctl_ctl->mcfg);
268 /* DFI update configuration register */
269 writel(MCTL_DFIUPDCFG_UPD, &mctl_ctl->dfiupdcfg);
271 /* Move to access state */
272 writel(MCTL_SCTL_ACCESS, &mctl_ctl->sctl);
273 await_completion(&mctl_ctl->sstat, 0x07, 0x03);
276 static void mctl_com_init(struct dram_sun6i_para *para)
278 struct sunxi_mctl_com_reg * const mctl_com =
279 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
280 struct sunxi_mctl_phy_reg * const mctl_phy1 =
281 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
282 struct sunxi_prcm_reg * const prcm =
283 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
285 writel(MCTL_CR_UNKNOWN | MCTL_CR_CHANNEL(para->chan) | MCTL_CR_DDR3 |
286 ((para->bus_width == 32) ? MCTL_CR_BUSW32 : MCTL_CR_BUSW16) |
287 MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) |
288 MCTL_CR_BANK(1) | MCTL_CR_RANK(para->rank), &mctl_com->cr);
290 /* Unknown magic performed by boot0 */
291 setbits_le32(&mctl_com->dbgcr, (1 << 6));
293 if (para->chan == 1) {
294 /* Shutdown channel 1 */
295 setbits_le32(&mctl_phy1->aciocr, MCTL_ACIOCR_DISABLE);
296 setbits_le32(&mctl_phy1->dxccr, MCTL_DXCCR_DISABLE);
297 clrbits_le32(&mctl_phy1->dsgcr, MCTL_DSGCR_ENABLE);
299 * CH0 ?? this is what boot0 does. Leave as is until we can
302 setbits_le32(&prcm->vdd_sys_pwroff,
303 PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF);
307 static void mctl_port_cfg(void)
309 struct sunxi_mctl_com_reg * const mctl_com =
310 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
311 struct sunxi_ccm_reg * const ccm =
312 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
314 /* enable DRAM AXI clock for CPU access */
315 setbits_le32(&ccm->axi_gate, 1 << AXI_GATE_OFFSET_DRAM);
317 /* Bunch of magic writes performed by boot0 */
318 writel(0x00400302, &mctl_com->rmcr[0]);
319 writel(0x01000307, &mctl_com->rmcr[1]);
320 writel(0x00400302, &mctl_com->rmcr[2]);
321 writel(0x01000307, &mctl_com->rmcr[3]);
322 writel(0x01000307, &mctl_com->rmcr[4]);
323 writel(0x01000303, &mctl_com->rmcr[6]);
324 writel(0x01000303, &mctl_com->mmcr[0]);
325 writel(0x00400310, &mctl_com->mmcr[1]);
326 writel(0x01000307, &mctl_com->mmcr[2]);
327 writel(0x01000303, &mctl_com->mmcr[3]);
328 writel(0x01800303, &mctl_com->mmcr[4]);
329 writel(0x01800303, &mctl_com->mmcr[5]);
330 writel(0x01800303, &mctl_com->mmcr[6]);
331 writel(0x01800303, &mctl_com->mmcr[7]);
332 writel(0x01000303, &mctl_com->mmcr[8]);
333 writel(0x00000002, &mctl_com->mmcr[15]);
334 writel(0x00000310, &mctl_com->mbagcr[0]);
335 writel(0x00400310, &mctl_com->mbagcr[1]);
336 writel(0x00400310, &mctl_com->mbagcr[2]);
337 writel(0x00000307, &mctl_com->mbagcr[3]);
338 writel(0x00000317, &mctl_com->mbagcr[4]);
339 writel(0x00000307, &mctl_com->mbagcr[5]);
342 static bool mctl_mem_matches(u32 offset)
344 const int match_count = 64;
347 for (i = 0; i < match_count; i++) {
348 if (readl(CONFIG_SYS_SDRAM_BASE + i * 4) ==
349 readl(CONFIG_SYS_SDRAM_BASE + offset + i * 4))
353 return matches == match_count;
356 unsigned long sunxi_dram_init(void)
358 struct sunxi_mctl_com_reg * const mctl_com =
359 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
361 int bank, bus, columns;
363 /* Set initial parameters, these get modified by the autodetect code */
364 struct dram_sun6i_para para = {
372 /* A31s only has one channel */
373 if (sunxi_get_ss_bonding_id() == SUNXI_SS_BOND_ID_A31S)
378 mctl_dll_init(0, ¶);
379 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN);
381 if (para.chan == 2) {
382 mctl_dll_init(1, ¶);
383 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN);
386 setbits_le32(&mctl_com->ccr, MCTL_CCR_MASTER_CLK_EN);
388 mctl_channel_init(0, ¶);
390 mctl_channel_init(1, ¶);
392 mctl_com_init(¶);
396 * Change to 1 ch / sequence / 8192 byte pages / 16 rows /
397 * 8 bit banks / 1 rank mode.
399 clrsetbits_le32(&mctl_com->cr,
400 MCTL_CR_CHANNEL_MASK | MCTL_CR_PAGE_SIZE_MASK |
401 MCTL_CR_ROW_MASK | MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK,
402 MCTL_CR_CHANNEL(1) | MCTL_CR_SEQUENCE |
403 MCTL_CR_PAGE_SIZE(8192) | MCTL_CR_ROW(16) |
404 MCTL_CR_BANK(1) | MCTL_CR_RANK(1));
406 /* Detect and set page size */
407 for (columns = 7; columns < 20; columns++) {
408 if (mctl_mem_matches(1 << columns))
411 bus = (para.bus_width == 32) ? 2 : 1;
413 para.page_size = (1 << columns) * (bus << 1);
414 clrsetbits_le32(&mctl_com->cr, MCTL_CR_PAGE_SIZE_MASK,
415 MCTL_CR_PAGE_SIZE(para.page_size));
417 /* Detect and set rows */
418 for (para.rows = 11; para.rows < 16; para.rows++) {
419 offset = 1 << (para.rows + columns + bus);
420 if (mctl_mem_matches(offset))
423 clrsetbits_le32(&mctl_com->cr, MCTL_CR_ROW_MASK,
424 MCTL_CR_ROW(para.rows));
426 /* Detect bank size */
427 offset = 1 << (para.rows + columns + bus + 2);
428 bank = mctl_mem_matches(offset) ? 0 : 1;
430 /* Restore interleave, chan and rank values, set bank size */
431 clrsetbits_le32(&mctl_com->cr,
432 MCTL_CR_CHANNEL_MASK | MCTL_CR_SEQUENCE |
433 MCTL_CR_BANK_MASK | MCTL_CR_RANK_MASK,
434 MCTL_CR_CHANNEL(para.chan) | MCTL_CR_BANK(bank) |
435 MCTL_CR_RANK(para.rank));
437 return 1 << (para.rank + para.rows + bank + columns + para.chan + bus);