2 * sunxi DRAM controller initialization
3 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
6 * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
7 * and earlier U-Boot Allwiner A10 SPL work
9 * (C) Copyright 2007-2012
10 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
11 * Berg Xing <bergxing@allwinnertech.com>
12 * Tom Cubie <tangliang@allwinnertech.com>
14 * SPDX-License-Identifier: GPL-2.0+
18 * Unfortunately the only documentation we have on the sun7i DRAM
19 * controller is Allwinner boot0 + boot1 code, and that code uses
20 * magic numbers & shifts with no explanations. Hence this code is
21 * rather undocumented and full of magic.
26 #include <asm/arch/clock.h>
27 #include <asm/arch/dram.h>
28 #include <asm/arch/timer.h>
29 #include <asm/arch/sys_proto.h>
31 #define CPU_CFG_CHIP_VER(n) ((n) << 6)
32 #define CPU_CFG_CHIP_VER_MASK CPU_CFG_CHIP_VER(0x3)
33 #define CPU_CFG_CHIP_REV_A 0x0
34 #define CPU_CFG_CHIP_REV_C1 0x1
35 #define CPU_CFG_CHIP_REV_C2 0x2
36 #define CPU_CFG_CHIP_REV_B 0x3
39 * Wait up to 1s for value to be set in given part of reg.
41 static void await_completion(u32 *reg, u32 mask, u32 val)
43 unsigned long tmo = timer_get_us() + 1000000;
45 while ((readl(reg) & mask) != val) {
46 if (timer_get_us() > tmo)
47 panic("Timeout initialising DRAM\n");
52 * Wait up to 1s for mask to be clear in given reg.
54 static inline void await_bits_clear(u32 *reg, u32 mask)
56 await_completion(reg, mask, 0);
60 * Wait up to 1s for mask to be set in given reg.
62 static inline void await_bits_set(u32 *reg, u32 mask)
64 await_completion(reg, mask, mask);
68 * This performs the external DRAM reset by driving the RESET pin low and
69 * then high again. According to the DDR3 spec, the RESET pin needs to be
70 * kept low for at least 200 us.
72 static void mctl_ddr3_reset(void)
74 struct sunxi_dram_reg *dram =
75 (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
77 #ifdef CONFIG_MACH_SUN4I
78 struct sunxi_timer_reg *timer =
79 (struct sunxi_timer_reg *)SUNXI_TIMER_BASE;
82 writel(0, &timer->cpu_cfg);
83 reg_val = readl(&timer->cpu_cfg);
85 if ((reg_val & CPU_CFG_CHIP_VER_MASK) !=
86 CPU_CFG_CHIP_VER(CPU_CFG_CHIP_REV_A)) {
87 setbits_le32(&dram->mcr, DRAM_MCR_RESET);
89 clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
93 clrbits_le32(&dram->mcr, DRAM_MCR_RESET);
95 setbits_le32(&dram->mcr, DRAM_MCR_RESET);
97 /* After the RESET pin is de-asserted, the DDR3 spec requires to wait
98 * for additional 500 us before driving the CKE pin (Clock Enable)
99 * high. The duration of this delay can be configured in the SDR_IDCR
100 * (Initialization Delay Configuration Register) and applied
101 * automatically by the DRAM controller during the DDR3 initialization
102 * step. But SDR_IDCR has limited range on sun4i/sun5i hardware and
103 * can't provide sufficient delay at DRAM clock frequencies higher than
104 * 524 MHz (while Allwinner A13 supports DRAM clock frequency up to
105 * 533 MHz according to the datasheet). Additionally, there is no
106 * official documentation for the SDR_IDCR register anywhere, and
107 * there is always a chance that we are interpreting it wrong.
108 * Better be safe than sorry, so add an explicit delay here. */
112 static void mctl_set_drive(void)
114 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
116 #ifdef CONFIG_MACH_SUN7I
117 clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28),
119 clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3),
121 DRAM_MCR_MODE_EN(0x3) |
125 static void mctl_itm_disable(void)
127 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
129 clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF);
132 static void mctl_itm_enable(void)
134 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
136 clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF);
139 static void mctl_itm_reset(void)
142 udelay(1); /* ITM reset needs a bit of delay */
147 static void mctl_enable_dll0(u32 phase)
149 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
151 clrsetbits_le32(&dram->dllcr[0], 0x3f << 6,
152 ((phase >> 16) & 0x3f) << 6);
153 clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET, DRAM_DLLCR_DISABLE);
156 clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE);
159 clrsetbits_le32(&dram->dllcr[0], DRAM_DLLCR_DISABLE, DRAM_DLLCR_NRESET);
163 /* Get the number of DDR byte lanes */
164 static u32 mctl_get_number_of_lanes(void)
166 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
167 if ((readl(&dram->dcr) & DRAM_DCR_BUS_WIDTH_MASK) ==
168 DRAM_DCR_BUS_WIDTH(DRAM_DCR_BUS_WIDTH_32BIT))
175 * Note: This differs from pm/standby in that it checks the bus width
177 static void mctl_enable_dllx(u32 phase)
179 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
180 u32 i, number_of_lanes;
182 number_of_lanes = mctl_get_number_of_lanes();
184 for (i = 1; i <= number_of_lanes; i++) {
185 clrsetbits_le32(&dram->dllcr[i], 0xf << 14,
186 (phase & 0xf) << 14);
187 clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET,
193 for (i = 1; i <= number_of_lanes; i++)
194 clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET |
198 for (i = 1; i <= number_of_lanes; i++)
199 clrsetbits_le32(&dram->dllcr[i], DRAM_DLLCR_DISABLE,
204 static u32 hpcr_value[32] = {
205 #ifdef CONFIG_MACH_SUN5I
210 0x1031, 0x1031, 0x0735, 0x1035,
211 0x1035, 0x0731, 0x1031, 0,
212 0x0301, 0x0301, 0x0301, 0x0301,
213 0x0301, 0x0301, 0x0301, 0
215 #ifdef CONFIG_MACH_SUN4I
216 0x0301, 0x0301, 0x0301, 0x0301,
217 0x0301, 0x0301, 0, 0,
220 0x1031, 0x1031, 0x0735, 0x5031,
221 0x1035, 0x0731, 0x1031, 0x0735,
222 0x1035, 0x1031, 0x0731, 0x1035,
223 0x1031, 0x0301, 0x0301, 0x0731
225 #ifdef CONFIG_MACH_SUN7I
226 0x0301, 0x0301, 0x0301, 0x0301,
227 0x0301, 0x0301, 0x0301, 0x0301,
230 0x1031, 0x1031, 0x0735, 0x1035,
231 0x1035, 0x0731, 0x1031, 0x0735,
232 0x1035, 0x1031, 0x0731, 0x1035,
233 0x0001, 0x1031, 0, 0x1031
234 /* last row differs from boot0 source table
235 * 0x1031, 0x0301, 0x0301, 0x0731
236 * but boot0 code skips #28 and #30, and sets #29 and #31 to the
237 * value from #28 entry (0x1031)
242 static void mctl_configure_hostport(void)
244 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
247 for (i = 0; i < 32; i++)
248 writel(hpcr_value[i], &dram->hpcr[i]);
251 static void mctl_setup_dram_clock(u32 clk, u32 mbus_clk)
254 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
255 u32 pll5p_clk, pll6x_clk;
256 u32 pll5p_div, pll6x_div;
257 u32 pll5p_rate, pll6x_rate;
260 reg_val = readl(&ccm->pll5_cfg);
261 reg_val &= ~CCM_PLL5_CTRL_M_MASK; /* set M to 0 (x1) */
262 reg_val &= ~CCM_PLL5_CTRL_K_MASK; /* set K to 0 (x1) */
263 reg_val &= ~CCM_PLL5_CTRL_N_MASK; /* set N to 0 (x0) */
264 reg_val &= ~CCM_PLL5_CTRL_P_MASK; /* set P to 0 (x1) */
265 #ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT
266 /* Old kernels are hardcoded to P=1 (divide by 2) */
267 reg_val |= CCM_PLL5_CTRL_P(1);
269 if (clk >= 540 && clk < 552) {
271 reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
272 reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
273 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(15));
274 } else if (clk >= 512 && clk < 528) {
276 reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
277 reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(4));
278 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(16));
279 } else if (clk >= 496 && clk < 504) {
281 reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(3));
282 reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
283 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(31));
284 } else if (clk >= 468 && clk < 480) {
286 reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
287 reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
288 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(13));
289 } else if (clk >= 396 && clk < 408) {
291 reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
292 reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(3));
293 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(11));
295 /* any other frequency that is a multiple of 24 */
296 reg_val |= CCM_PLL5_CTRL_M(CCM_PLL5_CTRL_M_X(2));
297 reg_val |= CCM_PLL5_CTRL_K(CCM_PLL5_CTRL_K_X(2));
298 reg_val |= CCM_PLL5_CTRL_N(CCM_PLL5_CTRL_N_X(clk / 24));
300 reg_val &= ~CCM_PLL5_CTRL_VCO_GAIN; /* PLL VCO Gain off */
301 reg_val |= CCM_PLL5_CTRL_EN; /* PLL On */
302 writel(reg_val, &ccm->pll5_cfg);
305 setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK);
307 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
309 clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE);
310 setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
312 clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS);
315 /* setup MBUS clock */
319 /* PLL5P and PLL6 are the potential clock sources for MBUS */
320 pll6x_clk = clock_get_pll6() / 1000000;
321 #ifdef CONFIG_MACH_SUN7I
322 pll6x_clk *= 2; /* sun7i uses PLL6*2, sun5i uses just PLL6 */
324 pll5p_clk = clock_get_pll5p() / 1000000;
325 pll6x_div = DIV_ROUND_UP(pll6x_clk, mbus_clk);
326 pll5p_div = DIV_ROUND_UP(pll5p_clk, mbus_clk);
327 pll6x_rate = pll6x_clk / pll6x_div;
328 pll5p_rate = pll5p_clk / pll5p_div;
330 if (pll6x_div <= 16 && pll6x_rate > pll5p_rate) {
331 /* use PLL6 as the MBUS clock source */
332 reg_val = CCM_MBUS_CTRL_GATE |
333 CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL6) |
334 CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
335 CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(pll6x_div));
336 } else if (pll5p_div <= 16) {
337 /* use PLL5P as the MBUS clock source */
338 reg_val = CCM_MBUS_CTRL_GATE |
339 CCM_MBUS_CTRL_CLK_SRC(CCM_MBUS_CTRL_CLK_SRC_PLL5) |
340 CCM_MBUS_CTRL_N(CCM_MBUS_CTRL_N_X(1)) |
341 CCM_MBUS_CTRL_M(CCM_MBUS_CTRL_M_X(pll5p_div));
343 panic("Bad mbus_clk\n");
345 writel(reg_val, &ccm->mbus_clk_cfg);
348 * open DRAMC AHB & DLL register clock
351 #if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
352 clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
354 clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
359 #if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
360 setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL);
362 setbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM);
368 * The data from rslrX and rdgrX registers (X=rank) is stored
369 * in a single 32-bit value using the following format:
370 * bits [31:26] - DQS gating system latency for byte lane 3
371 * bits [25:24] - DQS gating phase select for byte lane 3
372 * bits [23:18] - DQS gating system latency for byte lane 2
373 * bits [17:16] - DQS gating phase select for byte lane 2
374 * bits [15:10] - DQS gating system latency for byte lane 1
375 * bits [ 9:8 ] - DQS gating phase select for byte lane 1
376 * bits [ 7:2 ] - DQS gating system latency for byte lane 0
377 * bits [ 1:0 ] - DQS gating phase select for byte lane 0
379 static void mctl_set_dqs_gating_delay(int rank, u32 dqs_gating_delay)
381 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
382 u32 lane, number_of_lanes = mctl_get_number_of_lanes();
383 /* rank0 gating system latency (3 bits per lane: cycles) */
384 u32 slr = readl(rank == 0 ? &dram->rslr0 : &dram->rslr1);
385 /* rank0 gating phase select (2 bits per lane: 90, 180, 270, 360) */
386 u32 dgr = readl(rank == 0 ? &dram->rdgr0 : &dram->rdgr1);
387 for (lane = 0; lane < number_of_lanes; lane++) {
388 u32 tmp = dqs_gating_delay >> (lane * 8);
389 slr &= ~(7 << (lane * 3));
390 slr |= ((tmp >> 2) & 7) << (lane * 3);
391 dgr &= ~(3 << (lane * 2));
392 dgr |= (tmp & 3) << (lane * 2);
394 writel(slr, rank == 0 ? &dram->rslr0 : &dram->rslr1);
395 writel(dgr, rank == 0 ? &dram->rdgr0 : &dram->rdgr1);
398 static int dramc_scan_readpipe(void)
400 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
403 /* data training trigger */
404 clrbits_le32(&dram->csr, DRAM_CSR_FAILED);
405 setbits_le32(&dram->ccr, DRAM_CCR_DATA_TRAINING);
407 /* check whether data training process has completed */
408 await_bits_clear(&dram->ccr, DRAM_CCR_DATA_TRAINING);
410 /* check data training result */
411 reg_val = readl(&dram->csr);
412 if (reg_val & DRAM_CSR_FAILED)
418 static void dramc_clock_output_en(u32 on)
420 #if defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
421 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
424 setbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
426 clrbits_le32(&dram->mcr, DRAM_MCR_DCLK_OUT);
428 #ifdef CONFIG_MACH_SUN4I
429 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
431 setbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
433 clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAM_CTRL_DCLK_OUT);
437 /* tRFC in nanoseconds for different densities (from the DDR3 spec) */
438 static const u16 tRFC_DDR3_table[6] = {
439 /* 256Mb 512Mb 1Gb 2Gb 4Gb 8Gb */
440 90, 90, 110, 160, 300, 350
443 static void dramc_set_autorefresh_cycle(u32 clk, u32 density)
445 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
448 tRFC = (tRFC_DDR3_table[density] * clk + 999) / 1000;
449 tREFI = (7987 * clk) >> 10; /* <= 7.8us */
451 writel(DRAM_DRR_TREFI(tREFI) | DRAM_DRR_TRFC(tRFC), &dram->drr);
454 /* Calculate the value for A11, A10, A9 bits in MR0 (write recovery) */
455 static u32 ddr3_write_recovery(u32 clk)
457 u32 twr_ns = 15; /* DDR3 spec says that it is 15ns for all speed bins */
458 u32 twr_ck = (twr_ns * clk + 999) / 1000;
461 else if (twr_ck <= 8)
463 else if (twr_ck <= 10)
470 * If the dram->ppwrsctl (SDR_DPCR) register has the lowest bit set to 1, this
471 * means that DRAM is currently in self-refresh mode and retaining the old
472 * data. Since we have no idea what to do in this situation yet, just set this
473 * register to 0 and initialize DRAM in the same way as on any normal reboot
474 * (discarding whatever was stored there).
476 * Note: on sun7i hardware, the highest 16 bits need to be set to 0x1651 magic
477 * value for this write operation to have any effect. On sun5i hadware this
478 * magic value is not necessary. And on sun4i hardware the writes to this
479 * register seem to have no effect at all.
481 static void mctl_disable_power_save(void)
483 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
484 writel(0x16510000, &dram->ppwrsctl);
488 * After the DRAM is powered up or reset, the DDR3 spec requires to wait at
489 * least 500 us before driving the CKE pin (Clock Enable) high. The dram->idct
490 * (SDR_IDCR) register appears to configure this delay, which gets applied
491 * right at the time when the DRAM initialization is activated in the
492 * 'mctl_ddr3_initialize' function.
494 static void mctl_set_cke_delay(void)
496 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
498 /* The CKE delay is represented in DRAM clock cycles, multiplied by N
499 * (where N=2 for sun4i/sun5i and N=3 for sun7i). Here it is set to
500 * the maximum possible value 0x1ffff, just like in the Allwinner's
501 * boot0 bootloader. The resulting delay value is somewhere between
502 * ~0.4 ms (sun5i with 648 MHz DRAM clock speed) and ~1.1 ms (sun7i
503 * with 360 MHz DRAM clock speed). */
504 setbits_le32(&dram->idcr, 0x1ffff);
508 * This triggers the DRAM initialization. It performs sending the mode registers
509 * to the DRAM among other things. Very likely the ZQCL command is also getting
510 * executed (to do the initial impedance calibration on the DRAM side of the
511 * wire). The memory controller and the PHY must be already configured before
512 * calling this function.
514 static void mctl_ddr3_initialize(void)
516 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
517 setbits_le32(&dram->ccr, DRAM_CCR_INIT);
518 await_bits_clear(&dram->ccr, DRAM_CCR_INIT);
522 * Perform impedance calibration on the DRAM controller side of the wire.
524 static void mctl_set_impedance(u32 zq, u32 odt_en)
526 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
528 u32 zprog = zq & 0xFF, zdata = (zq >> 8) & 0xFFFFF;
530 #ifndef CONFIG_MACH_SUN7I
531 /* Appears that some kind of automatically initiated default
532 * ZQ calibration is already in progress at this point on sun4i/sun5i
533 * hardware, but not on sun7i. So it is reasonable to wait for its
534 * completion before doing anything else. */
535 await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);
538 /* ZQ calibration is not really useful unless ODT is enabled */
542 #ifdef CONFIG_MACH_SUN7I
543 /* Enabling ODT in SDR_IOCR on sun7i hardware results in a deadlock
544 * unless bit 24 is set in SDR_ZQCR1. Not much is known about the
545 * SDR_ZQCR1 register, but there are hints indicating that it might
546 * be related to periodic impedance re-calibration. This particular
547 * magic value is borrowed from the Allwinner boot0 bootloader, and
548 * using it helps to avoid troubles */
549 writel((1 << 24) | (1 << 1), &dram->zqcr1);
552 /* Needed at least for sun5i, because it does not self clear there */
553 clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL);
556 /* Set the user supplied impedance data */
557 reg_val = DRAM_ZQCR0_ZDEN | zdata;
558 writel(reg_val, &dram->zqcr0);
559 /* no need to wait, this takes effect immediately */
561 /* Do the calibration using the external resistor */
562 reg_val = DRAM_ZQCR0_ZCAL | DRAM_ZQCR0_IMP_DIV(zprog);
563 writel(reg_val, &dram->zqcr0);
564 /* Wait for the new impedance configuration to settle */
565 await_bits_set(&dram->zqsr, DRAM_ZQSR_ZDONE);
568 /* Needed at least for sun5i, because it does not self clear there */
569 clrbits_le32(&dram->zqcr0, DRAM_ZQCR0_ZCAL);
571 /* Set I/O configure register */
572 writel(DRAM_IOCR_ODT_EN(odt_en), &dram->iocr);
575 static unsigned long dramc_init_helper(struct dram_para *para)
577 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE;
583 * only single rank DDR3 is supported by this code even though the
584 * hardware can theoretically support DDR2 and up to two ranks
586 if (para->type != DRAM_MEMORY_TYPE_DDR3 || para->rank_num != 1)
589 /* setup DRAM relative clock */
590 mctl_setup_dram_clock(para->clock, para->mbus_clock);
592 /* Disable any pad power save control */
593 mctl_disable_power_save();
598 dramc_clock_output_en(0);
600 #ifdef CONFIG_MACH_SUN4I
601 /* select dram controller 1 */
602 writel(DRAM_CSEL_MAGIC, &dram->csel);
606 mctl_enable_dll0(para->tpr3);
608 /* configure external DRAM */
609 reg_val = DRAM_DCR_TYPE_DDR3;
610 reg_val |= DRAM_DCR_IO_WIDTH(para->io_width >> 3);
612 if (para->density == 256)
613 density = DRAM_DCR_CHIP_DENSITY_256M;
614 else if (para->density == 512)
615 density = DRAM_DCR_CHIP_DENSITY_512M;
616 else if (para->density == 1024)
617 density = DRAM_DCR_CHIP_DENSITY_1024M;
618 else if (para->density == 2048)
619 density = DRAM_DCR_CHIP_DENSITY_2048M;
620 else if (para->density == 4096)
621 density = DRAM_DCR_CHIP_DENSITY_4096M;
622 else if (para->density == 8192)
623 density = DRAM_DCR_CHIP_DENSITY_8192M;
625 density = DRAM_DCR_CHIP_DENSITY_256M;
627 reg_val |= DRAM_DCR_CHIP_DENSITY(density);
628 reg_val |= DRAM_DCR_BUS_WIDTH((para->bus_width >> 3) - 1);
629 reg_val |= DRAM_DCR_RANK_SEL(para->rank_num - 1);
630 reg_val |= DRAM_DCR_CMD_RANK_ALL;
631 reg_val |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE);
632 writel(reg_val, &dram->dcr);
634 dramc_clock_output_en(1);
636 mctl_set_impedance(para->zq, para->odt_en);
638 mctl_set_cke_delay();
644 await_bits_clear(&dram->ccr, DRAM_CCR_INIT);
646 mctl_enable_dllx(para->tpr3);
648 /* set refresh period */
649 dramc_set_autorefresh_cycle(para->clock, density);
651 /* set timing parameters */
652 writel(para->tpr0, &dram->tpr0);
653 writel(para->tpr1, &dram->tpr1);
654 writel(para->tpr2, &dram->tpr2);
656 reg_val = DRAM_MR_BURST_LENGTH(0x0);
657 #if (defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I))
658 reg_val |= DRAM_MR_POWER_DOWN;
660 reg_val |= DRAM_MR_CAS_LAT(para->cas - 4);
661 reg_val |= DRAM_MR_WRITE_RECOVERY(ddr3_write_recovery(para->clock));
662 writel(reg_val, &dram->mr);
664 writel(para->emr1, &dram->emr);
665 writel(para->emr2, &dram->emr2);
666 writel(para->emr3, &dram->emr3);
668 /* disable drift compensation and set passive DQS window mode */
669 clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
671 #ifdef CONFIG_MACH_SUN7I
672 /* Command rate timing mode 2T & 1T */
673 if (para->tpr4 & 0x1)
674 setbits_le32(&dram->ccr, DRAM_CCR_COMMAND_RATE_1T);
676 /* initialize external DRAM */
677 mctl_ddr3_initialize();
679 /* scan read pipe value */
682 /* Hardware DQS gate training */
683 ret_val = dramc_scan_readpipe();
688 /* allow to override the DQS training results with a custom delay */
689 if (para->dqs_gating_delay)
690 mctl_set_dqs_gating_delay(0, para->dqs_gating_delay);
692 /* set the DQS gating window type */
693 if (para->active_windowing)
694 clrbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE);
696 setbits_le32(&dram->ccr, DRAM_CCR_DQS_GATE);
700 /* configure all host port */
701 mctl_configure_hostport();
703 return get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
706 unsigned long dramc_init(struct dram_para *para)
708 unsigned long dram_size, actual_density;
710 /* If the dram configuration is not provided, use a default */
714 /* if everything is known, then autodetection is not necessary */
715 if (para->io_width && para->bus_width && para->density)
716 return dramc_init_helper(para);
718 /* try to autodetect the DRAM bus width and density */
720 para->bus_width = 32;
721 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I)
722 /* only A0-A14 address lines on A10/A13, limiting max density to 4096 */
723 para->density = 4096;
725 /* all A0-A15 address lines on A20, which allow density 8192 */
726 para->density = 8192;
729 dram_size = dramc_init_helper(para);
731 /* if 32-bit bus width failed, try 16-bit bus width instead */
732 para->bus_width = 16;
733 dram_size = dramc_init_helper(para);
735 /* if 16-bit bus width also failed, then bail out */
740 /* check if we need to adjust the density */
741 actual_density = (dram_size >> 17) * para->io_width / para->bus_width;
743 if (actual_density != para->density) {
744 /* update the density and re-initialize DRAM again */
745 para->density = actual_density;
746 dram_size = dramc_init_helper(para);