2 * sun6i specific clock code
4 * (C) Copyright 2007-2012
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Tom Cubie <tangliang@allwinnertech.com>
8 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
10 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/clock.h>
16 #include <asm/arch/prcm.h>
17 #include <asm/arch/sys_proto.h>
19 #ifdef CONFIG_SPL_BUILD
20 void clock_init_safe(void)
22 struct sunxi_ccm_reg * const ccm =
23 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
24 struct sunxi_prcm_reg * const prcm =
25 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
27 /* Set PLL ldo voltage without this PLL6 does not work properly */
28 clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
29 PRCM_PLL_CTRL_LDO_KEY);
30 clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
31 PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
32 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
33 clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
35 clock_set_pll1(408000000);
37 writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
39 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
41 writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
42 writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
46 void clock_init_uart(void)
48 #if CONFIG_CONS_INDEX < 5
49 struct sunxi_ccm_reg *const ccm =
50 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
52 /* uart clock source is apb2 */
53 writel(APB2_CLK_SRC_OSC24M|
58 /* open the clock for uart */
59 setbits_le32(&ccm->apb2_gate,
60 CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
61 CONFIG_CONS_INDEX - 1));
63 /* deassert uart reset */
64 setbits_le32(&ccm->apb2_reset_cfg,
65 1 << (APB2_RESET_UART_SHIFT +
66 CONFIG_CONS_INDEX - 1));
68 /* enable R_PIO and R_UART clocks, and de-assert resets */
69 prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
73 int clock_twi_onoff(int port, int state)
75 struct sunxi_ccm_reg *const ccm =
76 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
81 /* set the apb clock gate for twi */
83 setbits_le32(&ccm->apb2_gate,
84 CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
86 clrbits_le32(&ccm->apb2_gate,
87 CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
92 #ifdef CONFIG_SPL_BUILD
93 void clock_set_pll1(unsigned int clk)
95 struct sunxi_ccm_reg * const ccm =
96 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
101 if (clk > 1152000000) {
103 } else if (clk > 768000000) {
108 /* Switch to 24MHz clock while changing PLL1 */
109 writel(AXI_DIV_3 << AXI_DIV_SHIFT |
110 ATB_DIV_2 << ATB_DIV_SHIFT |
111 CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
115 * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored)
116 * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m
118 writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
119 CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
120 CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
123 /* Switch CPU to PLL1 */
124 writel(AXI_DIV_3 << AXI_DIV_SHIFT |
125 ATB_DIV_2 << ATB_DIV_SHIFT |
126 CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
131 void clock_set_pll3(unsigned int clk)
133 struct sunxi_ccm_reg * const ccm =
134 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
135 const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
138 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
142 /* PLL3 rate = 24000000 * n / m */
143 writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
144 CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
148 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
150 struct sunxi_ccm_reg * const ccm =
151 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
152 const int max_n = 32;
155 if (sigma_delta_enable)
156 writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
158 /* PLL5 rate = 24000000 * n * k / m */
159 if (clk > 24000000 * k * max_n / m) {
161 if (clk > 24000000 * k * max_n / m)
164 writel(CCM_PLL5_CTRL_EN |
165 (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) |
167 CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
168 CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
173 #ifdef CONFIG_MACH_SUN6I
174 void clock_set_mipi_pll(unsigned int clk)
176 struct sunxi_ccm_reg * const ccm =
177 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
178 unsigned int k, m, n, value, diff;
179 unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff;
180 unsigned int src = clock_get_pll3();
182 /* All calculations are in KHz to avoid overflows */
186 /* Pick the closest lower clock */
187 for (k = 1; k <= 4; k++) {
188 for (m = 1; m <= 16; m++) {
189 for (n = 1; n <= 16; n++) {
190 value = src * n * k / m;
195 if (diff < best_diff) {
208 writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN |
209 CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) |
210 CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg);
214 #ifdef CONFIG_MACH_SUN8I_A33
215 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
217 struct sunxi_ccm_reg * const ccm =
218 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
220 if (sigma_delta_enable)
221 writel(CCM_PLL11_PATTERN, &ccm->pll5_pattern_cfg);
223 writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
224 (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
225 CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);
227 while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)
232 unsigned int clock_get_pll3(void)
234 struct sunxi_ccm_reg *const ccm =
235 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
236 uint32_t rval = readl(&ccm->pll3_cfg);
237 int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1;
238 int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1;
240 /* Multiply by 1000 after dividing by m to avoid integer overflows */
241 return (24000 * n / m) * 1000;
244 unsigned int clock_get_pll6(void)
246 struct sunxi_ccm_reg *const ccm =
247 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
248 uint32_t rval = readl(&ccm->pll6_cfg);
249 int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
250 int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
251 return 24000000 * n * k / 2;
254 unsigned int clock_get_mipi_pll(void)
256 struct sunxi_ccm_reg *const ccm =
257 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
258 uint32_t rval = readl(&ccm->mipi_pll_cfg);
259 unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1;
260 unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1;
261 unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1;
262 unsigned int src = clock_get_pll3();
264 /* Multiply by 1000 after dividing by m to avoid integer overflows */
265 return ((src / 1000) * n * k / m) * 1000;
268 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
270 int pll = clock_get_pll6() * 2;
273 while ((pll / div) > hz)
276 writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),