2 * sun6i specific clock code
4 * (C) Copyright 2007-2012
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Tom Cubie <tangliang@allwinnertech.com>
8 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
10 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/clock.h>
16 #include <asm/arch/prcm.h>
17 #include <asm/arch/sys_proto.h>
19 #ifdef CONFIG_SPL_BUILD
20 void clock_init_safe(void)
22 struct sunxi_ccm_reg * const ccm =
23 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
24 struct sunxi_prcm_reg * const prcm =
25 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
27 /* Set PLL ldo voltage without this PLL6 does not work properly */
28 clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
29 PRCM_PLL_CTRL_LDO_KEY);
30 clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
31 PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
32 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
33 clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
35 clock_set_pll1(408000000);
37 writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
39 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
41 writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
42 writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
46 void clock_init_uart(void)
48 struct sunxi_ccm_reg *const ccm =
49 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
51 #if CONFIG_CONS_INDEX < 5
52 /* uart clock source is apb2 */
53 writel(APB2_CLK_SRC_OSC24M|
58 /* open the clock for uart */
59 setbits_le32(&ccm->apb2_gate,
60 CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
61 CONFIG_CONS_INDEX - 1));
63 /* deassert uart reset */
64 setbits_le32(&ccm->apb2_reset_cfg,
65 1 << (APB2_RESET_UART_SHIFT +
66 CONFIG_CONS_INDEX - 1));
68 /* enable R_PIO and R_UART clocks, and de-assert resets */
69 prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
72 /* Dup with clock_init_safe(), drop once sun6i SPL support lands */
73 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
76 int clock_twi_onoff(int port, int state)
78 struct sunxi_ccm_reg *const ccm =
79 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
84 /* set the apb clock gate for twi */
86 setbits_le32(&ccm->apb2_gate,
87 CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
89 clrbits_le32(&ccm->apb2_gate,
90 CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
95 #ifdef CONFIG_SPL_BUILD
96 void clock_set_pll1(unsigned int clk)
98 struct sunxi_ccm_reg * const ccm =
99 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
103 if (clk > 1152000000) {
105 } else if (clk > 768000000) {
110 /* Switch to 24MHz clock while changing PLL1 */
111 writel(AXI_DIV_3 << AXI_DIV_SHIFT |
112 ATB_DIV_2 << ATB_DIV_SHIFT |
113 CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
116 /* PLL1 rate = 24000000 * n * k / m */
117 writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_MAGIC |
118 CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
119 CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
122 /* Switch CPU to PLL1 */
123 writel(AXI_DIV_3 << AXI_DIV_SHIFT |
124 ATB_DIV_2 << ATB_DIV_SHIFT |
125 CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
130 void clock_set_pll5(unsigned int clk)
132 struct sunxi_ccm_reg * const ccm =
133 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
137 /* PLL5 rate = 24000000 * n * k / m */
138 writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD |
139 CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
140 CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
145 unsigned int clock_get_pll6(void)
147 struct sunxi_ccm_reg *const ccm =
148 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
149 uint32_t rval = readl(&ccm->pll6_cfg);
150 int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
151 int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
152 return 24000000 * n * k / 2;