2 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2007-2011
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Tom Cubie <tangliang@allwinnertech.com>
8 * Some init for sunxi platform.
10 * SPDX-License-Identifier: GPL-2.0+
17 #ifdef CONFIG_SPL_BUILD
22 #include <asm/arch/clock.h>
23 #include <asm/arch/gpio.h>
24 #include <asm/arch/sys_proto.h>
25 #include <asm/arch/timer.h>
26 #include <asm/arch/mmc.h>
28 #include <linux/compiler.h>
39 struct fel_stash fel_stash __attribute__((section(".data")));
41 static int gpio_init(void)
43 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
44 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
45 /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
46 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
47 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
49 #if defined(CONFIG_MACH_SUN8I)
50 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
51 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
53 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
54 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
56 sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
57 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
58 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
59 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
60 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
61 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
62 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
63 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
64 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
65 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
66 sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
67 sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
68 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
69 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
70 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
71 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
72 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
73 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
74 sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
75 sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
76 sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
77 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
78 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
79 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
80 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
81 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
82 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
83 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
84 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
85 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
86 sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
87 sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
88 sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
90 #error Unsupported console port number. Please fix pin mux settings in board.c
96 void spl_board_load_image(void)
98 debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
99 return_to_fel(fel_stash.sp, fel_stash.lr);
104 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23
105 /* Magic (undocmented) value taken from boot0, without this DRAM
106 * access gets messed up (seems cache related) */
107 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
109 #if defined CONFIG_MACH_SUN6I || \
110 defined CONFIG_MACH_SUN7I || \
111 defined CONFIG_MACH_SUN8I
112 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
114 "mrc p15, 0, r0, c1, c0, 1\n"
115 "orr r0, r0, #1 << 6\n"
116 "mcr p15, 0, r0, c1, c0, 1\n");
125 #ifdef CONFIG_SPL_BUILD
126 DECLARE_GLOBAL_DATA_PTR;
128 /* The sunxi internal brom will try to loader external bootloader
129 * from mmc0, nand flash, mmc2.
131 u32 spl_boot_device(void)
133 struct mmc *mmc0, *mmc1;
135 * When booting from the SD card or NAND memory, the "eGON.BT0"
136 * signature is expected to be found in memory at the address 0x0004
137 * (see the "mksunxiboot" tool, which generates this header).
139 * When booting in the FEL mode over USB, this signature is patched in
140 * memory and replaced with something else by the 'fel' tool. This other
141 * signature is selected in such a way, that it can't be present in a
142 * valid bootable SD card image (because the BROM would refuse to
143 * execute the SPL in this case).
145 * This checks for the signature and if it is not found returns to
146 * the FEL code in the BROM to wait and receive the main u-boot
147 * binary over USB. If it is found, it determines where SPL was
150 if (readl(4) != 0x4E4F4765 || readl(8) != 0x3054422E) /* eGON.BT0 */
151 return BOOT_DEVICE_BOARD;
153 /* The BROM will try to boot from mmc0 first, so try that first. */
154 mmc_initialize(gd->bd);
155 mmc0 = find_mmc_device(0);
156 if (sunxi_mmc_has_egon_boot_signature(mmc0))
157 return BOOT_DEVICE_MMC1;
159 /* Fallback to booting NAND if enabled. */
160 if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT))
161 return BOOT_DEVICE_NAND;
163 if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) {
164 mmc1 = find_mmc_device(1);
165 if (sunxi_mmc_has_egon_boot_signature(mmc1)) {
167 * spl_mmc.c: spl_mmc_load_image() is hard-coded to
168 * use find_mmc_device(0), no matter what we
169 * return. Swap mmc0 and mmc2 to make this work.
171 mmc0->block_dev.dev = 1;
172 mmc1->block_dev.dev = 0;
173 return BOOT_DEVICE_MMC2;
177 panic("Could not determine boot source\n");
178 return -1; /* Never reached */
181 /* No confirmation data available in SPL yet. Hardcode bootmode */
182 u32 spl_boot_mode(void)
184 return MMCSD_MODE_RAW;
187 void board_init_f(ulong dummy)
189 preloader_console_init();
191 #ifdef CONFIG_SPL_I2C_SUPPORT
192 /* Needed early by sunxi_board_init if PMU is enabled */
193 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
198 memset(__bss_start, 0, __bss_end - __bss_start);
200 board_init_r(NULL, 0);
204 void reset_cpu(ulong addr)
206 #ifdef CONFIG_SUNXI_GEN_SUN4I
207 static const struct sunxi_wdog *wdog =
208 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
210 /* Set the watchdog for its shortest interval (.5s) and wait */
211 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
212 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
215 /* sun5i sometimes gets stuck without this */
216 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
219 #ifdef CONFIG_SUNXI_GEN_SUN6I
220 static const struct sunxi_wdog *wdog =
221 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
223 /* Set the watchdog for its shortest interval (.5s) and wait */
224 writel(WDT_CFG_RESET, &wdog->cfg);
225 writel(WDT_MODE_EN, &wdog->mode);
226 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
231 #ifndef CONFIG_SYS_DCACHE_OFF
232 void enable_caches(void)
234 /* Enable D-cache. I-cache is already enabled in start.S */
239 #ifdef CONFIG_CMD_NET
241 * Initializes on-chip ethernet controllers.
242 * to override, implement board_eth_init()
244 int cpu_eth_init(bd_t *bis)
246 __maybe_unused int rc;
249 gpio_request(CONFIG_MACPWR, "macpwr");
250 gpio_direction_output(CONFIG_MACPWR, 1);
254 #ifdef CONFIG_SUNXI_GMAC
255 rc = sunxi_gmac_initialize(bis);
257 printf("sunxi: failed to initialize gmac\n");