2 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2007-2011
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Tom Cubie <tangliang@allwinnertech.com>
8 * Some init for sunxi platform.
10 * SPDX-License-Identifier: GPL-2.0+
18 #ifdef CONFIG_SPL_BUILD
23 #include <asm/arch/clock.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/arch/timer.h>
28 #include <linux/compiler.h>
30 #ifdef CONFIG_SPL_BUILD
31 /* Pointer to the global data structure for SPL */
32 DECLARE_GLOBAL_DATA_PTR;
34 /* The sunxi internal brom will try to loader external bootloader
35 * from mmc0, nand flash, mmc2.
36 * Unfortunately we can't check how SPL was loaded so assume
37 * it's always the first SD/MMC controller
39 u32 spl_boot_device(void)
41 return BOOT_DEVICE_MMC1;
44 /* No confirmation data available in SPL yet. Hardcode bootmode */
45 u32 spl_boot_mode(void)
47 return MMCSD_MODE_RAW;
53 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
54 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
55 /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
56 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
57 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
59 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX);
60 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX);
61 sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
62 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
63 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
64 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
65 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
66 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
67 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
68 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
69 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
70 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
71 sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX);
72 sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX);
73 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
74 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
75 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
76 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
77 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
78 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
79 sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
80 sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
81 sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
83 #error Unsupported console port number. Please fix pin mux settings in board.c
89 void reset_cpu(ulong addr)
91 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
92 static const struct sunxi_wdog *wdog =
93 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
95 /* Set the watchdog for its shortest interval (.5s) and wait */
96 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
97 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
100 /* sun5i sometimes gets stuck without this */
101 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
103 #else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || .. */
104 static const struct sunxi_wdog *wdog =
105 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
107 /* Set the watchdog for its shortest interval (.5s) and wait */
108 writel(WDT_CFG_RESET, &wdog->cfg);
109 writel(WDT_MODE_EN, &wdog->mode);
110 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
114 /* do some early init */
117 #if defined CONFIG_SPL_BUILD && \
118 (defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
119 /* Magic (undocmented) value taken from boot0, without this DRAM
120 * access gets messed up (seems cache related) */
121 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
123 #if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
124 defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
125 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
127 "mrc p15, 0, r0, c1, c0, 1\n"
128 "orr r0, r0, #1 << 6\n"
129 "mcr p15, 0, r0, c1, c0, 1\n");
137 #ifdef CONFIG_SPL_BUILD
139 preloader_console_init();
141 #ifdef CONFIG_SPL_I2C_SUPPORT
142 /* Needed early by sunxi_board_init if PMU is enabled */
143 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
149 #ifndef CONFIG_SYS_DCACHE_OFF
150 void enable_caches(void)
152 /* Enable D-cache. I-cache is already enabled in start.S */
157 #ifdef CONFIG_CMD_NET
159 * Initializes on-chip ethernet controllers.
160 * to override, implement board_eth_init()
162 int cpu_eth_init(bd_t *bis)
164 __maybe_unused int rc;
167 gpio_direction_output(CONFIG_MACPWR, 1);
171 #ifdef CONFIG_SUNXI_EMAC
172 rc = sunxi_emac_initialize(bis);
174 printf("sunxi: failed to initialize emac\n");
179 #ifdef CONFIG_SUNXI_GMAC
180 rc = sunxi_gmac_initialize(bis);
182 printf("sunxi: failed to initialize gmac\n");