2 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2007-2011
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Tom Cubie <tangliang@allwinnertech.com>
8 * Some init for sunxi platform.
10 * SPDX-License-Identifier: GPL-2.0+
18 #ifdef CONFIG_SPL_BUILD
23 #include <asm/arch/clock.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm/arch/timer.h>
28 #include <linux/compiler.h>
35 struct fel_stash fel_stash __attribute__((section(".data")));
37 static int gpio_init(void)
39 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
40 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
41 /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
42 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
43 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
45 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX);
46 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX);
47 sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
48 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
49 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
50 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
51 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
52 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
53 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX);
54 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);
55 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
56 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
57 sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX);
58 sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX);
59 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
60 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
61 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
62 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
63 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
64 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
65 sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL2_R_UART_TX);
66 sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL3_R_UART_RX);
67 sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
69 #error Unsupported console port number. Please fix pin mux settings in board.c
75 void spl_board_load_image(void)
77 debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
78 return_to_fel(fel_stash.sp, fel_stash.lr);
83 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
84 /* Magic (undocmented) value taken from boot0, without this DRAM
85 * access gets messed up (seems cache related) */
86 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
88 #if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
89 defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
90 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
92 "mrc p15, 0, r0, c1, c0, 1\n"
93 "orr r0, r0, #1 << 6\n"
94 "mcr p15, 0, r0, c1, c0, 1\n");
103 #ifdef CONFIG_SPL_BUILD
104 /* The sunxi internal brom will try to loader external bootloader
105 * from mmc0, nand flash, mmc2.
106 * Unfortunately we can't check how SPL was loaded so assume
107 * it's always the first SD/MMC controller
109 u32 spl_boot_device(void)
112 * Have we been asked to return to the FEL portion of the boot ROM?
113 * TODO: We need a more robust test here, or bracket this with
114 * #ifdef CONFIG_SPL_FEL.
116 if (fel_stash.lr >= 0xffff0000 && fel_stash.lr < 0xffff4000)
117 return BOOT_DEVICE_BOARD;
119 return BOOT_DEVICE_MMC1;
122 /* No confirmation data available in SPL yet. Hardcode bootmode */
123 u32 spl_boot_mode(void)
125 return MMCSD_MODE_RAW;
128 void board_init_f(ulong dummy)
130 preloader_console_init();
132 #ifdef CONFIG_SPL_I2C_SUPPORT
133 /* Needed early by sunxi_board_init if PMU is enabled */
134 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
139 memset(__bss_start, 0, __bss_end - __bss_start);
141 board_init_r(NULL, 0);
145 void reset_cpu(ulong addr)
147 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
148 static const struct sunxi_wdog *wdog =
149 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
151 /* Set the watchdog for its shortest interval (.5s) and wait */
152 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
153 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
156 /* sun5i sometimes gets stuck without this */
157 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
159 #else /* CONFIG_MACH_SUN6I || CONFIG_MACH_SUN8I || .. */
160 static const struct sunxi_wdog *wdog =
161 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
163 /* Set the watchdog for its shortest interval (.5s) and wait */
164 writel(WDT_CFG_RESET, &wdog->cfg);
165 writel(WDT_MODE_EN, &wdog->mode);
166 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
170 #ifndef CONFIG_SYS_DCACHE_OFF
171 void enable_caches(void)
173 /* Enable D-cache. I-cache is already enabled in start.S */
178 #ifdef CONFIG_CMD_NET
180 * Initializes on-chip ethernet controllers.
181 * to override, implement board_eth_init()
183 int cpu_eth_init(bd_t *bis)
185 __maybe_unused int rc;
188 gpio_direction_output(CONFIG_MACPWR, 1);
192 #ifdef CONFIG_SUNXI_EMAC
193 rc = sunxi_emac_initialize(bis);
195 printf("sunxi: failed to initialize emac\n");
200 #ifdef CONFIG_SUNXI_GMAC
201 rc = sunxi_gmac_initialize(bis);
203 printf("sunxi: failed to initialize gmac\n");