2 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2007-2011
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Tom Cubie <tangliang@allwinnertech.com>
8 * Some init for sunxi platform.
10 * SPDX-License-Identifier: GPL-2.0+
15 #ifdef CONFIG_SPL_BUILD
20 #include <asm/arch/clock.h>
21 #include <asm/arch/gpio.h>
22 #include <asm/arch/sys_proto.h>
23 #include <asm/arch/timer.h>
25 #ifdef CONFIG_SPL_BUILD
26 /* Pointer to the global data structure for SPL */
27 DECLARE_GLOBAL_DATA_PTR;
29 /* The sunxi internal brom will try to loader external bootloader
30 * from mmc0, nand flash, mmc2.
31 * Unfortunately we can't check how SPL was loaded so assume
32 * it's always the first SD/MMC controller
34 u32 spl_boot_device(void)
36 return BOOT_DEVICE_MMC1;
39 /* No confirmation data available in SPL yet. Hardcode bootmode */
40 u32 spl_boot_mode(void)
42 return MMCSD_MODE_RAW;
48 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX);
49 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX);
50 sunxi_gpio_set_pull(SUNXI_GPB(23), 1);
55 void reset_cpu(ulong addr)
59 /* do some early init */
62 #if !defined CONFIG_SPL_BUILD && (defined CONFIG_SUN7I || defined CONFIG_SUN6I)
63 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
65 "mrc p15, 0, r0, c1, c0, 1\n"
66 "orr r0, r0, #1 << 6\n"
67 "mcr p15, 0, r0, c1, c0, 1\n");
74 #ifdef CONFIG_SPL_BUILD
76 preloader_console_init();
82 #ifndef CONFIG_SYS_DCACHE_OFF
83 void enable_caches(void)
85 /* Enable D-cache. I-cache is already enabled in start.S */