2 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2007-2011
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Tom Cubie <tangliang@allwinnertech.com>
8 * Some init for sunxi platform.
10 * SPDX-License-Identifier: GPL-2.0+
17 #ifdef CONFIG_SPL_BUILD
22 #include <asm/arch/clock.h>
23 #include <asm/arch/gpio.h>
24 #include <asm/arch/sys_proto.h>
25 #include <asm/arch/timer.h>
26 #include <asm/arch/tzpc.h>
27 #include <asm/arch/mmc.h>
29 #include <linux/compiler.h>
40 struct fel_stash fel_stash __attribute__((section(".data")));
42 static int gpio_init(void)
44 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
45 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
46 /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
47 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
48 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
50 #if defined(CONFIG_MACH_SUN8I)
51 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
52 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
54 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
55 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
57 sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
58 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
59 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
60 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
61 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
62 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
63 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
64 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
65 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
66 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
67 sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
68 sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
69 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
70 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
71 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
72 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
73 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
74 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
75 sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
76 sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
77 sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
78 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
79 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
80 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
81 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
82 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
83 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
84 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
85 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
86 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
87 sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
88 sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
89 sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
91 #error Unsupported console port number. Please fix pin mux settings in board.c
97 void spl_board_load_image(void)
99 debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
100 return_to_fel(fel_stash.sp, fel_stash.lr);
105 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23
106 /* Magic (undocmented) value taken from boot0, without this DRAM
107 * access gets messed up (seems cache related) */
108 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
110 #if defined CONFIG_MACH_SUN6I || \
111 defined CONFIG_MACH_SUN7I || \
112 defined CONFIG_MACH_SUN8I
113 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
115 "mrc p15, 0, r0, c1, c0, 1\n"
116 "orr r0, r0, #1 << 6\n"
117 "mcr p15, 0, r0, c1, c0, 1\n");
119 #if defined CONFIG_MACH_SUN6I
120 /* Enable non-secure access to the RTC */
130 #ifdef CONFIG_SPL_BUILD
131 DECLARE_GLOBAL_DATA_PTR;
133 /* The sunxi internal brom will try to loader external bootloader
134 * from mmc0, nand flash, mmc2.
136 u32 spl_boot_device(void)
138 struct mmc *mmc0, *mmc1;
140 * When booting from the SD card or NAND memory, the "eGON.BT0"
141 * signature is expected to be found in memory at the address 0x0004
142 * (see the "mksunxiboot" tool, which generates this header).
144 * When booting in the FEL mode over USB, this signature is patched in
145 * memory and replaced with something else by the 'fel' tool. This other
146 * signature is selected in such a way, that it can't be present in a
147 * valid bootable SD card image (because the BROM would refuse to
148 * execute the SPL in this case).
150 * This checks for the signature and if it is not found returns to
151 * the FEL code in the BROM to wait and receive the main u-boot
152 * binary over USB. If it is found, it determines where SPL was
155 if (readl(4) != 0x4E4F4765 || readl(8) != 0x3054422E) /* eGON.BT0 */
156 return BOOT_DEVICE_BOARD;
158 /* The BROM will try to boot from mmc0 first, so try that first. */
159 mmc_initialize(gd->bd);
160 mmc0 = find_mmc_device(0);
161 if (sunxi_mmc_has_egon_boot_signature(mmc0))
162 return BOOT_DEVICE_MMC1;
164 /* Fallback to booting NAND if enabled. */
165 if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT))
166 return BOOT_DEVICE_NAND;
168 if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) {
169 mmc1 = find_mmc_device(1);
170 if (sunxi_mmc_has_egon_boot_signature(mmc1)) {
172 * spl_mmc.c: spl_mmc_load_image() is hard-coded to
173 * use find_mmc_device(0), no matter what we
174 * return. Swap mmc0 and mmc2 to make this work.
176 mmc0->block_dev.dev = 1;
177 mmc1->block_dev.dev = 0;
178 return BOOT_DEVICE_MMC2;
182 panic("Could not determine boot source\n");
183 return -1; /* Never reached */
186 /* No confirmation data available in SPL yet. Hardcode bootmode */
187 u32 spl_boot_mode(void)
189 return MMCSD_MODE_RAW;
192 void board_init_f(ulong dummy)
194 preloader_console_init();
196 #ifdef CONFIG_SPL_I2C_SUPPORT
197 /* Needed early by sunxi_board_init if PMU is enabled */
198 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
203 memset(__bss_start, 0, __bss_end - __bss_start);
205 board_init_r(NULL, 0);
209 void reset_cpu(ulong addr)
211 #ifdef CONFIG_SUNXI_GEN_SUN4I
212 static const struct sunxi_wdog *wdog =
213 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
215 /* Set the watchdog for its shortest interval (.5s) and wait */
216 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
217 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
220 /* sun5i sometimes gets stuck without this */
221 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
224 #ifdef CONFIG_SUNXI_GEN_SUN6I
225 static const struct sunxi_wdog *wdog =
226 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
228 /* Set the watchdog for its shortest interval (.5s) and wait */
229 writel(WDT_CFG_RESET, &wdog->cfg);
230 writel(WDT_MODE_EN, &wdog->mode);
231 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
236 #ifndef CONFIG_SYS_DCACHE_OFF
237 void enable_caches(void)
239 /* Enable D-cache. I-cache is already enabled in start.S */
244 #ifdef CONFIG_CMD_NET
246 * Initializes on-chip ethernet controllers.
247 * to override, implement board_eth_init()
249 int cpu_eth_init(bd_t *bis)
251 __maybe_unused int rc;
254 gpio_request(CONFIG_MACPWR, "macpwr");
255 gpio_direction_output(CONFIG_MACPWR, 1);
259 #ifdef CONFIG_SUNXI_GMAC
260 rc = sunxi_gmac_initialize(bis);
262 printf("sunxi: failed to initialize gmac\n");