2 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2007-2011
5 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
6 * Tom Cubie <tangliang@allwinnertech.com>
8 * Some init for sunxi platform.
10 * SPDX-License-Identifier: GPL-2.0+
16 #ifdef CONFIG_SPL_BUILD
21 #include <asm/arch/clock.h>
22 #include <asm/arch/gpio.h>
23 #include <asm/arch/sys_proto.h>
24 #include <asm/arch/timer.h>
26 #include <linux/compiler.h>
37 struct fel_stash fel_stash __attribute__((section(".data")));
39 static int gpio_init(void)
41 #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
42 #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
43 /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
44 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
45 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
47 #if defined(CONFIG_MACH_SUN8I)
48 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
49 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
51 sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
52 sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
54 sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
55 #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
56 sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
57 sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
58 sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
59 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
60 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
61 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
62 sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
63 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
64 sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
65 sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
66 sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
67 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
68 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
69 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
70 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
71 #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
72 sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
73 sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
74 sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
75 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
76 sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
77 sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
78 sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
79 #elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
80 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
81 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
82 sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
83 #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
84 sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
85 sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
86 sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
88 #error Unsupported console port number. Please fix pin mux settings in board.c
94 void spl_board_load_image(void)
96 debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
97 return_to_fel(fel_stash.sp, fel_stash.lr);
102 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23
103 /* Magic (undocmented) value taken from boot0, without this DRAM
104 * access gets messed up (seems cache related) */
105 setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
107 #if defined CONFIG_MACH_SUN6I || \
108 defined CONFIG_MACH_SUN7I || \
109 defined CONFIG_MACH_SUN8I
110 /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
112 "mrc p15, 0, r0, c1, c0, 1\n"
113 "orr r0, r0, #1 << 6\n"
114 "mcr p15, 0, r0, c1, c0, 1\n");
123 #ifdef CONFIG_SPL_BUILD
124 /* The sunxi internal brom will try to loader external bootloader
125 * from mmc0, nand flash, mmc2.
126 * Unfortunately we can't check how SPL was loaded so assume
127 * it's always the first SD/MMC controller
129 u32 spl_boot_device(void)
132 * When booting from the SD card, the "eGON.BT0" signature is expected
133 * to be found in memory at the address 0x0004 (see the "mksunxiboot"
134 * tool, which generates this header).
136 * When booting in the FEL mode over USB, this signature is patched in
137 * memory and replaced with something else by the 'fel' tool. This other
138 * signature is selected in such a way, that it can't be present in a
139 * valid bootable SD card image (because the BROM would refuse to
140 * execute the SPL in this case).
142 * This branch is just making a decision at runtime whether to load
143 * the main u-boot binary from the SD card (if the "eGON.BT0" signature
144 * is found) or return to the FEL code in the BROM to wait and receive
145 * the main u-boot binary over USB.
147 if (readl(4) == 0x4E4F4765 && readl(8) == 0x3054422E) /* eGON.BT0 */
148 return BOOT_DEVICE_MMC1;
150 return BOOT_DEVICE_BOARD;
153 /* No confirmation data available in SPL yet. Hardcode bootmode */
154 u32 spl_boot_mode(void)
156 return MMCSD_MODE_RAW;
159 void board_init_f(ulong dummy)
161 preloader_console_init();
163 #ifdef CONFIG_SPL_I2C_SUPPORT
164 /* Needed early by sunxi_board_init if PMU is enabled */
165 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
170 memset(__bss_start, 0, __bss_end - __bss_start);
172 board_init_r(NULL, 0);
176 void reset_cpu(ulong addr)
178 #ifdef CONFIG_SUNXI_GEN_SUN4I
179 static const struct sunxi_wdog *wdog =
180 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
182 /* Set the watchdog for its shortest interval (.5s) and wait */
183 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
184 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
187 /* sun5i sometimes gets stuck without this */
188 writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
191 #ifdef CONFIG_SUNXI_GEN_SUN6I
192 static const struct sunxi_wdog *wdog =
193 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
195 /* Set the watchdog for its shortest interval (.5s) and wait */
196 writel(WDT_CFG_RESET, &wdog->cfg);
197 writel(WDT_MODE_EN, &wdog->mode);
198 writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
203 #ifndef CONFIG_SYS_DCACHE_OFF
204 void enable_caches(void)
206 /* Enable D-cache. I-cache is already enabled in start.S */
211 #ifdef CONFIG_CMD_NET
213 * Initializes on-chip ethernet controllers.
214 * to override, implement board_eth_init()
216 int cpu_eth_init(bd_t *bis)
218 __maybe_unused int rc;
221 gpio_request(CONFIG_MACPWR, "macpwr");
222 gpio_direction_output(CONFIG_MACPWR, 1);
226 #ifdef CONFIG_SUNXI_GMAC
227 rc = sunxi_gmac_initialize(bis);
229 printf("sunxi: failed to initialize gmac\n");