2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm-offsets.h>
38 ldr pc, _undefined_instruction
39 ldr pc, _software_interrupt
40 ldr pc, _prefetch_abort
46 _undefined_instruction: .word undefined_instruction
47 _software_interrupt: .word software_interrupt
48 _prefetch_abort: .word prefetch_abort
49 _data_abort: .word data_abort
50 _not_used: .word not_used
53 _pad: .word 0x12345678 /* now 16*4=64 */
57 .balignl 16,0xdeadbeef
58 /*************************************************************************
60 * Startup Code (reset vector)
62 * do important init only if we don't start from memory!
63 * setup Memory and board specific bits prior to relocation.
64 * relocate armboot to ram
67 *************************************************************************/
71 .word CONFIG_SYS_TEXT_BASE
74 * These are defined in the board-specific linker script.
78 .word __bss_start - _start
85 /* IRQ stack memory (calculated at run-time) */
86 .globl IRQ_STACK_START
90 /* IRQ stack memory (calculated at run-time) */
91 .globl FIQ_STACK_START
96 /* IRQ stack memory (calculated at run-time) + 8 bytes */
97 .globl IRQ_STACK_START_IN
101 .globl _datarel_start_ofs
103 .word __datarel_start - _start
105 .globl _datarelrolocal_start_ofs
106 _datarelrolocal_start_ofs:
107 .word __datarelrolocal_start - _start
109 .globl _datarellocal_start_ofs
110 _datarellocal_start_ofs:
111 .word __datarellocal_start - _start
113 .globl _datarelro_start_ofs
114 _datarelro_start_ofs:
115 .word __datarelro_start - _start
117 .globl _got_start_ofs
119 .word __got_start - _start
123 .word __got_end - _start
126 * the actual reset code
131 * set the cpu to SVC32 mode
138 #if (CONFIG_OMAP34XX)
139 /* Copy vectors to mask ROM indirect addr */
140 adr r0, _start @ r0 <- current position of code
141 add r0, r0, #4 @ skip reset vector
142 mov r2, #64 @ r2 <- size to copy
143 add r2, r0, r2 @ r2 <- source end address
144 mov r1, #SRAM_OFFSET0 @ build vect addr
145 mov r3, #SRAM_OFFSET1
147 mov r3, #SRAM_OFFSET2
150 ldmia r0!, {r3 - r10} @ copy from source address [r0]
151 stmia r1!, {r3 - r10} @ copy to target address [r1]
152 cmp r0, r2 @ until source end address [r2]
153 bne next @ loop until equal */
154 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
155 /* No need to copy/exec the clock code - DPLL adjust already done
156 * in NAND/oneNAND Boot.
158 bl cpy_clk_code @ put dpll adjust code behind vectors
159 #endif /* NAND Boot */
161 /* the mask ROM code should have PLL and others stable */
162 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
166 /* Set stackpointer in internal RAM to call board_init_f */
168 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
172 /*------------------------------------------------------------------------------*/
175 * void relocate_code (addr_sp, gd, addr_moni)
177 * This "function" does not return, instead it continues in RAM
178 * after relocating the monitor code.
183 mov r4, r0 /* save addr_sp */
184 mov r5, r1 /* save addr of gd */
185 mov r6, r2 /* save addr of destination */
186 mov r7, r2 /* save addr of destination */
188 /* Set up the stack */
194 ldr r3, _bss_start_ofs
195 add r2, r0, r3 /* r2 <- source end address */
197 #ifndef CONFIG_PRELOADER
202 ldmia r0!, {r9-r10} /* copy from source address [r0] */
203 stmia r6!, {r9-r10} /* copy to target address [r1] */
204 cmp r0, r2 /* until source end address [r2] */
207 #ifndef CONFIG_PRELOADER
209 * fix .rel.dyn relocations
211 ldr r0, _TEXT_BASE /* r0 <- Text base */
212 sub r9, r7, r0 /* r9 <- relocation offset */
213 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
214 add r10, r10, r0 /* r10 <- sym table in FLASH */
215 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
216 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
217 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
218 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
220 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
221 add r0, r0, r9 /* r0 <- location to fix up in RAM */
224 cmp r8, #23 /* relative fixup? */
226 cmp r8, #2 /* absolute fixup? */
228 /* ignore unknown type of fixup */
231 /* absolute fix: set location to (offset) symbol value */
232 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
233 add r1, r10, r1 /* r1 <- address of symbol in table */
234 ldr r1, [r1, #4] /* r1 <- symbol value */
235 add r1, r9 /* r1 <- relocated sym addr */
238 /* relative fix: increase location by offset */
243 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
248 ldr r0, _bss_start_ofs
250 ldr r3, _TEXT_BASE /* Text base */
251 mov r4, r7 /* reloc addr */
254 mov r2, #0x00000000 /* clear */
256 clbss_l:str r2, [r0] /* clear loop... */
260 #endif /* #ifndef CONFIG_PRELOADER */
263 * We are done. Do not return, instead branch to second part of board
264 * initialization, now running from RAM.
267 ldr r0, _board_init_r_ofs
271 /* setup parameters for board_init_r */
272 mov r0, r5 /* gd_t */
273 mov r1, r7 /* dest_addr */
278 .word board_init_r - _start
281 .word __rel_dyn_start - _start
283 .word __rel_dyn_end - _start
285 .word __dynsym_start - _start
287 /*************************************************************************
289 * CPU_init_critical registers
291 * setup important registers
292 * setup memory timing
294 *************************************************************************/
299 mov r0, #0 @ set up for MCR
300 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
301 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
304 * disable MMU stuff and caches
306 mrc p15, 0, r0, c1, c0, 0
307 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
308 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
309 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
310 orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB
311 mcr p15, 0, r0, c1, c0, 0
314 * Jump to board specific initialization...
315 * The Mask ROM will have already initialized
316 * basic memory. Go here to bump up clock rate and handle
317 * wake up conditions.
319 mov ip, lr @ persevere link reg across call
320 bl lowlevel_init @ go setup pll,mux,memory
321 mov lr, ip @ restore link
322 mov pc, lr @ back to my caller
324 *************************************************************************
328 *************************************************************************
333 #define S_FRAME_SIZE 72
355 #define MODE_SVC 0x13
359 * use bad_save_user_regs for abort/prefetch/undef/swi ...
360 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
363 .macro bad_save_user_regs
364 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
366 stmia sp, {r0 - r12} @ Save user registers (now in
368 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
370 ldmia r2, {r2 - r3} @ get values for "aborted" pc
371 @ and cpsr (into parm regs)
372 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
376 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
377 mov r0, sp @ save current stack into r0
381 .macro irq_save_user_regs
382 sub sp, sp, #S_FRAME_SIZE
383 stmia sp, {r0 - r12} @ Calling r0-r12
384 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
385 @ a reserved stack spot would
387 stmdb r8, {sp, lr}^ @ Calling SP, LR
388 str lr, [r8, #0] @ Save calling PC
390 str r6, [r8, #4] @ Save CPSR
391 str r0, [r8, #8] @ Save OLD_R0
395 .macro irq_restore_user_regs
396 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
398 ldr lr, [sp, #S_PC] @ Get PC
399 add sp, sp, #S_FRAME_SIZE
400 subs pc, lr, #4 @ return & move spsr_svc into
405 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
408 str lr, [r13] @ save caller lr in position 0
410 mrs lr, spsr @ get the spsr
411 str lr, [r13, #4] @ save spsr in position 1 of
414 mov r13, #MODE_SVC @ prepare SVC-Mode
416 msr spsr, r13 @ switch modes, make sure
418 mov lr, pc @ capture return pc
419 movs pc, lr @ jump to next instruction &
423 .macro get_bad_stack_swi
424 sub r13, r13, #4 @ space on current stack for
426 str r0, [r13] @ save R0's value.
427 ldr r0, IRQ_STACK_START_IN @ get data regions start
428 @ spots for abort stack
429 str lr, [r0] @ save caller lr in position 0
431 mrs r0, spsr @ get the spsr
432 str lr, [r0, #4] @ save spsr in position 1 of
434 ldr r0, [r13] @ restore r0
435 add r13, r13, #4 @ pop stack entry
438 .macro get_irq_stack @ setup IRQ stack
439 ldr sp, IRQ_STACK_START
442 .macro get_fiq_stack @ setup FIQ stack
443 ldr sp, FIQ_STACK_START
450 undefined_instruction:
453 bl do_undefined_instruction
459 bl do_software_interrupt
479 #ifdef CONFIG_USE_IRQ
486 irq_restore_user_regs
491 /* someone ought to write a more effective fiq_save_user_regs */
494 irq_restore_user_regs