2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
13 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm-offsets.h>
19 #include <asm/system.h>
20 #include <linux/linkage.h>
24 ldr pc, _undefined_instruction
25 ldr pc, _software_interrupt
26 ldr pc, _prefetch_abort
31 #ifdef CONFIG_SPL_BUILD
32 _undefined_instruction: .word _undefined_instruction
33 _software_interrupt: .word _software_interrupt
34 _prefetch_abort: .word _prefetch_abort
35 _data_abort: .word _data_abort
36 _not_used: .word _not_used
39 _pad: .word 0x12345678 /* now 16*4=64 */
41 .globl _undefined_instruction
42 _undefined_instruction: .word undefined_instruction
43 .globl _software_interrupt
44 _software_interrupt: .word software_interrupt
45 .globl _prefetch_abort
46 _prefetch_abort: .word prefetch_abort
48 _data_abort: .word data_abort
50 _not_used: .word not_used
55 _pad: .word 0x12345678 /* now 16*4=64 */
56 #endif /* CONFIG_SPL_BUILD */
61 .balignl 16,0xdeadbeef
62 /*************************************************************************
64 * Startup Code (reset vector)
66 * do important init only if we don't start from memory!
67 * setup Memory and board specific bits prior to relocation.
68 * relocate armboot to ram
71 *************************************************************************/
74 /* IRQ stack memory (calculated at run-time) */
75 .globl IRQ_STACK_START
79 /* IRQ stack memory (calculated at run-time) */
80 .globl FIQ_STACK_START
85 /* IRQ stack memory (calculated at run-time) + 8 bytes */
86 .globl IRQ_STACK_START_IN
91 * the actual reset code
97 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
98 * except if in HYP mode already
101 and r1, r0, #0x1f @ mask mode bits
102 teq r1, #0x1a @ test for HYP mode
103 bicne r0, r0, #0x1f @ clear all mode bits
104 orrne r0, r0, #0x13 @ set SVC mode
105 orr r0, r0, #0xc0 @ disable FIQ and IRQ
110 * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
111 * Continue to use ROM code vector only in OMAP4 spl)
113 #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
114 /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
115 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register
116 bic r0, #CR_V @ V = 0
117 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register
119 /* Set vector address in CP15 VBAR register */
121 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
124 /* the mask ROM code should have PLL and others stable */
125 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
132 /*------------------------------------------------------------------------------*/
134 ENTRY(c_runtime_cpu_setup)
136 * If I-cache is enabled invalidate it
138 #ifndef CONFIG_SYS_ICACHE_OFF
139 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
140 mcr p15, 0, r0, c7, c10, 4 @ DSB
141 mcr p15, 0, r0, c7, c5, 4 @ ISB
146 /* Set vector address in CP15 VBAR register */
148 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
152 ENDPROC(c_runtime_cpu_setup)
154 /*************************************************************************
156 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
157 * __attribute__((weak));
159 * Stack pointer is not yet initialized at this moment
160 * Don't save anything to stack even if compiled with -O0
162 *************************************************************************/
163 ENTRY(save_boot_params)
164 bx lr @ back to my caller
165 ENDPROC(save_boot_params)
166 .weak save_boot_params
168 /*************************************************************************
172 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
173 * CONFIG_SYS_ICACHE_OFF is defined.
175 *************************************************************************/
180 mov r0, #0 @ set up for MCR
181 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
182 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
183 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
184 mcr p15, 0, r0, c7, c10, 4 @ DSB
185 mcr p15, 0, r0, c7, c5, 4 @ ISB
188 * disable MMU stuff and caches
190 mrc p15, 0, r0, c1, c0, 0
191 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
192 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
193 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
194 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
195 #ifdef CONFIG_SYS_ICACHE_OFF
196 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
198 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
200 mcr p15, 0, r0, c1, c0, 0
202 #ifdef CONFIG_ARM_ERRATA_716044
203 mrc p15, 0, r0, c1, c0, 0 @ read system control register
204 orr r0, r0, #1 << 11 @ set bit #11
205 mcr p15, 0, r0, c1, c0, 0 @ write system control register
208 #ifdef CONFIG_ARM_ERRATA_742230
209 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
210 orr r0, r0, #1 << 4 @ set bit #4
211 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
214 #ifdef CONFIG_ARM_ERRATA_743622
215 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
216 orr r0, r0, #1 << 6 @ set bit #6
217 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
220 #ifdef CONFIG_ARM_ERRATA_751472
221 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
222 orr r0, r0, #1 << 11 @ set bit #11
223 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
226 mov pc, lr @ back to my caller
227 ENDPROC(cpu_init_cp15)
229 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
230 /*************************************************************************
232 * CPU_init_critical registers
234 * setup important registers
235 * setup memory timing
237 *************************************************************************/
240 * Jump to board specific initialization...
241 * The Mask ROM will have already initialized
242 * basic memory. Go here to bump up clock rate and handle
243 * wake up conditions.
245 b lowlevel_init @ go setup pll,mux,memory
246 ENDPROC(cpu_init_crit)
249 #ifndef CONFIG_SPL_BUILD
251 *************************************************************************
255 *************************************************************************
260 #define S_FRAME_SIZE 72
282 #define MODE_SVC 0x13
286 * use bad_save_user_regs for abort/prefetch/undef/swi ...
287 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
290 .macro bad_save_user_regs
291 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
293 stmia sp, {r0 - r12} @ Save user registers (now in
295 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
297 ldmia r2, {r2 - r3} @ get values for "aborted" pc
298 @ and cpsr (into parm regs)
299 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
303 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
304 mov r0, sp @ save current stack into r0
308 .macro irq_save_user_regs
309 sub sp, sp, #S_FRAME_SIZE
310 stmia sp, {r0 - r12} @ Calling r0-r12
311 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
312 @ a reserved stack spot would
314 stmdb r8, {sp, lr}^ @ Calling SP, LR
315 str lr, [r8, #0] @ Save calling PC
317 str r6, [r8, #4] @ Save CPSR
318 str r0, [r8, #8] @ Save OLD_R0
322 .macro irq_restore_user_regs
323 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
325 ldr lr, [sp, #S_PC] @ Get PC
326 add sp, sp, #S_FRAME_SIZE
327 subs pc, lr, #4 @ return & move spsr_svc into
332 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
335 str lr, [r13] @ save caller lr in position 0
337 mrs lr, spsr @ get the spsr
338 str lr, [r13, #4] @ save spsr in position 1 of
341 mov r13, #MODE_SVC @ prepare SVC-Mode
343 msr spsr, r13 @ switch modes, make sure
345 mov lr, pc @ capture return pc
346 movs pc, lr @ jump to next instruction &
350 .macro get_bad_stack_swi
351 sub r13, r13, #4 @ space on current stack for
353 str r0, [r13] @ save R0's value.
354 ldr r0, IRQ_STACK_START_IN @ get data regions start
355 @ spots for abort stack
356 str lr, [r0] @ save caller lr in position 0
358 mrs lr, spsr @ get the spsr
359 str lr, [r0, #4] @ save spsr in position 1 of
361 ldr lr, [r0] @ restore lr
362 ldr r0, [r13] @ restore r0
363 add r13, r13, #4 @ pop stack entry
366 .macro get_irq_stack @ setup IRQ stack
367 ldr sp, IRQ_STACK_START
370 .macro get_fiq_stack @ setup FIQ stack
371 ldr sp, FIQ_STACK_START
378 undefined_instruction:
381 bl do_undefined_instruction
387 bl do_software_interrupt
407 #ifdef CONFIG_USE_IRQ
414 irq_restore_user_regs
419 /* someone ought to write a more effective fiq_save_user_regs */
422 irq_restore_user_regs
438 #endif /* CONFIG_USE_IRQ */
439 #endif /* CONFIG_SPL_BUILD */