2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
13 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm-offsets.h>
18 #include <asm/system.h>
19 #include <linux/linkage.h>
20 #include <asm/armv7.h>
22 /*************************************************************************
24 * Startup Code (reset vector)
26 * Do important init only if we don't start from memory!
27 * Setup memory and board specific bits prior to relocation.
28 * Relocate armboot to ram. Setup stack.
30 *************************************************************************/
33 .globl save_boot_params_ret
34 #ifdef CONFIG_ARMV7_LPAE
35 .global switch_to_hypervisor_ret
39 /* Allow the board to save important registers */
42 #ifdef CONFIG_ARMV7_LPAE
44 * check for Hypervisor support
46 mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
47 and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
48 cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT)
49 beq switch_to_hypervisor
50 switch_to_hypervisor_ret:
53 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
54 * except if in HYP mode already
57 and r1, r0, #0x1f @ mask mode bits
58 teq r1, #0x1a @ test for HYP mode
59 bicne r0, r0, #0x1f @ clear all mode bits
60 orrne r0, r0, #0x13 @ set SVC mode
61 orr r0, r0, #0xc0 @ disable FIQ and IRQ
66 * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
67 * Continue to use ROM code vector only in OMAP4 spl)
69 #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
70 /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
71 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register
73 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register
75 /* Set vector address in CP15 VBAR register */
77 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
80 /* the mask ROM code should have PLL and others stable */
81 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
83 #ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
90 /*------------------------------------------------------------------------------*/
92 ENTRY(c_runtime_cpu_setup)
94 * If I-cache is enabled invalidate it
96 #ifndef CONFIG_SYS_ICACHE_OFF
97 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
98 mcr p15, 0, r0, c7, c10, 4 @ DSB
99 mcr p15, 0, r0, c7, c5, 4 @ ISB
104 ENDPROC(c_runtime_cpu_setup)
106 /*************************************************************************
108 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
109 * __attribute__((weak));
111 * Stack pointer is not yet initialized at this moment
112 * Don't save anything to stack even if compiled with -O0
114 *************************************************************************/
115 ENTRY(save_boot_params)
116 b save_boot_params_ret @ back to my caller
117 ENDPROC(save_boot_params)
118 .weak save_boot_params
120 #ifdef CONFIG_ARMV7_LPAE
121 ENTRY(switch_to_hypervisor)
122 b switch_to_hypervisor_ret
123 ENDPROC(switch_to_hypervisor)
124 .weak switch_to_hypervisor
127 /*************************************************************************
131 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
132 * CONFIG_SYS_ICACHE_OFF is defined.
134 *************************************************************************/
139 mov r0, #0 @ set up for MCR
140 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
141 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
142 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
143 mcr p15, 0, r0, c7, c10, 4 @ DSB
144 mcr p15, 0, r0, c7, c5, 4 @ ISB
147 * disable MMU stuff and caches
149 mrc p15, 0, r0, c1, c0, 0
150 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
151 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
152 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
153 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
154 #ifdef CONFIG_SYS_ICACHE_OFF
155 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
157 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
159 mcr p15, 0, r0, c1, c0, 0
161 #ifdef CONFIG_ARM_ERRATA_716044
162 mrc p15, 0, r0, c1, c0, 0 @ read system control register
163 orr r0, r0, #1 << 11 @ set bit #11
164 mcr p15, 0, r0, c1, c0, 0 @ write system control register
167 #if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
168 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
169 orr r0, r0, #1 << 4 @ set bit #4
170 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
173 #ifdef CONFIG_ARM_ERRATA_743622
174 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
175 orr r0, r0, #1 << 6 @ set bit #6
176 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
179 #ifdef CONFIG_ARM_ERRATA_751472
180 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
181 orr r0, r0, #1 << 11 @ set bit #11
182 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
184 #ifdef CONFIG_ARM_ERRATA_761320
185 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
186 orr r0, r0, #1 << 21 @ set bit #21
187 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
190 #ifdef CONFIG_ARM_ERRATA_845369
191 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
192 orr r0, r0, #1 << 22 @ set bit #22
193 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
196 mov r5, lr @ Store my Caller
197 mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)
198 mov r3, r1, lsr #20 @ get variant field
199 and r3, r3, #0xf @ r3 has CPU variant
200 and r4, r1, #0xf @ r4 has CPU revision
201 mov r2, r3, lsl #4 @ shift variant field for combined value
202 orr r2, r4, r2 @ r2 has combined CPU variant + revision
204 #ifdef CONFIG_ARM_ERRATA_798870
205 cmp r2, #0x30 @ Applies to lower than R3p0
206 bge skip_errata_798870 @ skip if not affected rev
207 cmp r2, #0x20 @ Applies to including and above R2p0
208 blt skip_errata_798870 @ skip if not affected rev
210 mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg
211 orr r0, r0, #1 << 7 @ Enable hazard-detect timeout
212 push {r1-r5} @ Save the cpu info registers
213 bl v7_arch_cp15_set_l2aux_ctrl
214 isb @ Recommended ISB after l2actlr update
215 pop {r1-r5} @ Restore the cpu info - fall through
219 #ifdef CONFIG_ARM_ERRATA_801819
220 cmp r2, #0x24 @ Applies to lt including R2p4
221 bgt skip_errata_801819 @ skip if not affected rev
222 cmp r2, #0x20 @ Applies to including and above R2p0
223 blt skip_errata_801819 @ skip if not affected rev
224 mrc p15, 0, r0, c0, c0, 6 @ pick up REVIDR reg
225 and r0, r0, #1 << 3 @ check REVIDR[3]
227 beq skip_errata_801819 @ skip erratum if REVIDR[3] is set
229 mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register
230 orr r0, r0, #3 << 27 @ Disables streaming. All write-allocate
231 @ lines allocate in the L1 or L2 cache.
232 orr r0, r0, #3 << 25 @ Disables streaming. All write-allocate
233 @ lines allocate in the L1 cache.
234 push {r1-r5} @ Save the cpu info registers
235 bl v7_arch_cp15_set_acr
236 pop {r1-r5} @ Restore the cpu info - fall through
240 #ifdef CONFIG_ARM_ERRATA_454179
241 cmp r2, #0x21 @ Only on < r2p1
242 bge skip_errata_454179
244 mrc p15, 0, r0, c1, c0, 1 @ Read ACR
245 orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits
246 push {r1-r5} @ Save the cpu info registers
247 bl v7_arch_cp15_set_acr
248 pop {r1-r5} @ Restore the cpu info - fall through
253 #ifdef CONFIG_ARM_ERRATA_430973
254 cmp r2, #0x21 @ Only on < r2p1
255 bge skip_errata_430973
257 mrc p15, 0, r0, c1, c0, 1 @ Read ACR
258 orr r0, r0, #(0x1 << 6) @ Set IBE bit
259 push {r1-r5} @ Save the cpu info registers
260 bl v7_arch_cp15_set_acr
261 pop {r1-r5} @ Restore the cpu info - fall through
266 #ifdef CONFIG_ARM_ERRATA_621766
267 cmp r2, #0x21 @ Only on < r2p1
268 bge skip_errata_621766
270 mrc p15, 0, r0, c1, c0, 1 @ Read ACR
271 orr r0, r0, #(0x1 << 5) @ Set L1NEON bit
272 push {r1-r5} @ Save the cpu info registers
273 bl v7_arch_cp15_set_acr
274 pop {r1-r5} @ Restore the cpu info - fall through
279 #ifdef CONFIG_ARM_ERRATA_725233
280 cmp r2, #0x21 @ Only on < r2p1 (Cortex A8)
281 bge skip_errata_725233
283 mrc p15, 1, r0, c9, c0, 2 @ Read L2ACR
284 orr r0, r0, #(0x1 << 27) @ L2 PLD data forwarding disable
285 push {r1-r5} @ Save the cpu info registers
286 bl v7_arch_cp15_set_l2aux_ctrl
287 pop {r1-r5} @ Restore the cpu info - fall through
292 #ifdef CONFIG_ARM_ERRATA_852421
293 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
294 orr r0, r0, #1 << 24 @ set bit #24
295 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
298 #ifdef CONFIG_ARM_ERRATA_852423
299 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
300 orr r0, r0, #1 << 12 @ set bit #12
301 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
304 mov pc, r5 @ back to my caller
305 ENDPROC(cpu_init_cp15)
307 #if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
308 !defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
309 /*************************************************************************
311 * CPU_init_critical registers
313 * setup important registers
314 * setup memory timing
316 *************************************************************************/
319 * Jump to board specific initialization...
320 * The Mask ROM will have already initialized
321 * basic memory. Go here to bump up clock rate and handle
322 * wake up conditions.
324 b lowlevel_init @ go setup pll,mux,memory
325 ENDPROC(cpu_init_crit)