2 * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
4 * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
11 * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
13 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm-offsets.h>
19 #include <asm/system.h>
20 #include <linux/linkage.h>
24 ldr pc, _undefined_instruction
25 ldr pc, _software_interrupt
26 ldr pc, _prefetch_abort
31 #ifdef CONFIG_SPL_BUILD
32 _undefined_instruction: .word _undefined_instruction
33 _software_interrupt: .word _software_interrupt
34 _prefetch_abort: .word _prefetch_abort
35 _data_abort: .word _data_abort
36 _not_used: .word _not_used
39 _pad: .word 0x12345678 /* now 16*4=64 */
41 .globl _undefined_instruction
42 _undefined_instruction: .word undefined_instruction
43 .globl _software_interrupt
44 _software_interrupt: .word software_interrupt
45 .globl _prefetch_abort
46 _prefetch_abort: .word prefetch_abort
48 _data_abort: .word data_abort
50 _not_used: .word not_used
55 _pad: .word 0x12345678 /* now 16*4=64 */
56 #endif /* CONFIG_SPL_BUILD */
61 .balignl 16,0xdeadbeef
62 /*************************************************************************
64 * Startup Code (reset vector)
66 * do important init only if we don't start from memory!
67 * setup Memory and board specific bits prior to relocation.
68 * relocate armboot to ram
71 *************************************************************************/
75 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
76 .word CONFIG_SPL_TEXT_BASE
78 .word CONFIG_SYS_TEXT_BASE
82 * These are defined in the board-specific linker script.
86 .word __bss_start - _start
90 .word __bss_end - _start
97 /* IRQ stack memory (calculated at run-time) */
98 .globl IRQ_STACK_START
102 /* IRQ stack memory (calculated at run-time) */
103 .globl FIQ_STACK_START
108 /* IRQ stack memory (calculated at run-time) + 8 bytes */
109 .globl IRQ_STACK_START_IN
114 * the actual reset code
120 * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
121 * except if in HYP mode already
124 and r1, r0, #0x1f @ mask mode bits
125 teq r1, #0x1a @ test for HYP mode
126 bicne r0, r0, #0x1f @ clear all mode bits
127 orrne r0, r0, #0x13 @ set SVC mode
128 orr r0, r0, #0xc0 @ disable FIQ and IRQ
133 * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
134 * Continue to use ROM code vector only in OMAP4 spl)
136 #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
137 /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
138 mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTRL Register
139 bic r0, #CR_V @ V = 0
140 mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTRL Register
142 /* Set vector address in CP15 VBAR register */
144 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
147 /* the mask ROM code should have PLL and others stable */
148 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
155 /*------------------------------------------------------------------------------*/
157 ENTRY(c_runtime_cpu_setup)
159 * If I-cache is enabled invalidate it
161 #ifndef CONFIG_SYS_ICACHE_OFF
162 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
163 mcr p15, 0, r0, c7, c10, 4 @ DSB
164 mcr p15, 0, r0, c7, c5, 4 @ ISB
169 /* Set vector address in CP15 VBAR register */
171 mcr p15, 0, r0, c12, c0, 0 @Set VBAR
175 ENDPROC(c_runtime_cpu_setup)
177 /*************************************************************************
179 * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
180 * __attribute__((weak));
182 * Stack pointer is not yet initialized at this moment
183 * Don't save anything to stack even if compiled with -O0
185 *************************************************************************/
186 ENTRY(save_boot_params)
187 bx lr @ back to my caller
188 ENDPROC(save_boot_params)
189 .weak save_boot_params
191 /*************************************************************************
195 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
196 * CONFIG_SYS_ICACHE_OFF is defined.
198 *************************************************************************/
203 mov r0, #0 @ set up for MCR
204 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
205 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
206 mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
207 mcr p15, 0, r0, c7, c10, 4 @ DSB
208 mcr p15, 0, r0, c7, c5, 4 @ ISB
211 * disable MMU stuff and caches
213 mrc p15, 0, r0, c1, c0, 0
214 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
215 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
216 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
217 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
218 #ifdef CONFIG_SYS_ICACHE_OFF
219 bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
221 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
223 mcr p15, 0, r0, c1, c0, 0
225 #ifdef CONFIG_ARM_ERRATA_716044
226 mrc p15, 0, r0, c1, c0, 0 @ read system control register
227 orr r0, r0, #1 << 11 @ set bit #11
228 mcr p15, 0, r0, c1, c0, 0 @ write system control register
231 #ifdef CONFIG_ARM_ERRATA_742230
232 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
233 orr r0, r0, #1 << 4 @ set bit #4
234 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
237 #ifdef CONFIG_ARM_ERRATA_743622
238 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
239 orr r0, r0, #1 << 6 @ set bit #6
240 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
243 #ifdef CONFIG_ARM_ERRATA_751472
244 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
245 orr r0, r0, #1 << 11 @ set bit #11
246 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
249 mov pc, lr @ back to my caller
250 ENDPROC(cpu_init_cp15)
252 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
253 /*************************************************************************
255 * CPU_init_critical registers
257 * setup important registers
258 * setup memory timing
260 *************************************************************************/
263 * Jump to board specific initialization...
264 * The Mask ROM will have already initialized
265 * basic memory. Go here to bump up clock rate and handle
266 * wake up conditions.
268 b lowlevel_init @ go setup pll,mux,memory
269 ENDPROC(cpu_init_crit)
272 #ifndef CONFIG_SPL_BUILD
274 *************************************************************************
278 *************************************************************************
283 #define S_FRAME_SIZE 72
305 #define MODE_SVC 0x13
309 * use bad_save_user_regs for abort/prefetch/undef/swi ...
310 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
313 .macro bad_save_user_regs
314 sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
316 stmia sp, {r0 - r12} @ Save user registers (now in
318 ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
320 ldmia r2, {r2 - r3} @ get values for "aborted" pc
321 @ and cpsr (into parm regs)
322 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
326 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
327 mov r0, sp @ save current stack into r0
331 .macro irq_save_user_regs
332 sub sp, sp, #S_FRAME_SIZE
333 stmia sp, {r0 - r12} @ Calling r0-r12
334 add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
335 @ a reserved stack spot would
337 stmdb r8, {sp, lr}^ @ Calling SP, LR
338 str lr, [r8, #0] @ Save calling PC
340 str r6, [r8, #4] @ Save CPSR
341 str r0, [r8, #8] @ Save OLD_R0
345 .macro irq_restore_user_regs
346 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
348 ldr lr, [sp, #S_PC] @ Get PC
349 add sp, sp, #S_FRAME_SIZE
350 subs pc, lr, #4 @ return & move spsr_svc into
355 ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
358 str lr, [r13] @ save caller lr in position 0
360 mrs lr, spsr @ get the spsr
361 str lr, [r13, #4] @ save spsr in position 1 of
364 mov r13, #MODE_SVC @ prepare SVC-Mode
366 msr spsr, r13 @ switch modes, make sure
368 mov lr, pc @ capture return pc
369 movs pc, lr @ jump to next instruction &
373 .macro get_bad_stack_swi
374 sub r13, r13, #4 @ space on current stack for
376 str r0, [r13] @ save R0's value.
377 ldr r0, IRQ_STACK_START_IN @ get data regions start
378 @ spots for abort stack
379 str lr, [r0] @ save caller lr in position 0
381 mrs lr, spsr @ get the spsr
382 str lr, [r0, #4] @ save spsr in position 1 of
384 ldr lr, [r0] @ restore lr
385 ldr r0, [r13] @ restore r0
386 add r13, r13, #4 @ pop stack entry
389 .macro get_irq_stack @ setup IRQ stack
390 ldr sp, IRQ_STACK_START
393 .macro get_fiq_stack @ setup FIQ stack
394 ldr sp, FIQ_STACK_START
401 undefined_instruction:
404 bl do_undefined_instruction
410 bl do_software_interrupt
430 #ifdef CONFIG_USE_IRQ
437 irq_restore_user_regs
442 /* someone ought to write a more effective fiq_save_user_regs */
445 irq_restore_user_regs
461 #endif /* CONFIG_USE_IRQ */
462 #endif /* CONFIG_SPL_BUILD */