2 * Copyright (C) 2009 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Heungjun Kim <riverful.kim@samsung.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/clock.h>
28 #include <asm/arch/clk.h>
34 #ifndef CONFIG_SYS_CLK_FREQ_C100
35 #define CONFIG_SYS_CLK_FREQ_C100 12000000
37 #ifndef CONFIG_SYS_CLK_FREQ_C110
38 #define CONFIG_SYS_CLK_FREQ_C110 24000000
41 unsigned long (*get_uart_clk)(int dev_index);
42 unsigned long (*get_pwm_clk)(void);
43 unsigned long (*get_arm_clk)(void);
44 unsigned long (*get_pll_clk)(int);
46 /* s5pc110: return pll clock frequency */
47 static unsigned long s5pc100_get_pll_clk(int pllreg)
49 struct s5pc100_clock *clk =
50 (struct s5pc100_clock *)samsung_get_base_clock();
51 unsigned long r, m, p, s, mask, fout;
56 r = readl(&clk->apll_con);
59 r = readl(&clk->mpll_con);
62 r = readl(&clk->epll_con);
65 r = readl(&clk->hpll_con);
68 printf("Unsupported PLL (%d)\n", pllreg);
73 * APLL_CON: MIDV [25:16]
74 * MPLL_CON: MIDV [23:16]
75 * EPLL_CON: MIDV [23:16]
76 * HPLL_CON: MIDV [23:16]
90 /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
91 freq = CONFIG_SYS_CLK_FREQ_C100;
92 fout = m * (freq / (p * (1 << s)));
97 /* s5pc100: return pll clock frequency */
98 static unsigned long s5pc110_get_pll_clk(int pllreg)
100 struct s5pc110_clock *clk =
101 (struct s5pc110_clock *)samsung_get_base_clock();
102 unsigned long r, m, p, s, mask, fout;
107 r = readl(&clk->apll_con);
110 r = readl(&clk->mpll_con);
113 r = readl(&clk->epll_con);
116 r = readl(&clk->vpll_con);
119 printf("Unsupported PLL (%d)\n", pllreg);
124 * APLL_CON: MIDV [25:16]
125 * MPLL_CON: MIDV [25:16]
126 * EPLL_CON: MIDV [24:16]
127 * VPLL_CON: MIDV [24:16]
129 if (pllreg == APLL || pllreg == MPLL)
134 m = (r >> 16) & mask;
141 freq = CONFIG_SYS_CLK_FREQ_C110;
142 if (pllreg == APLL) {
145 /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
146 fout = m * (freq / (p * (1 << (s - 1))));
148 /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
149 fout = m * (freq / (p * (1 << s)));
154 /* s5pc110: return ARM clock frequency */
155 static unsigned long s5pc110_get_arm_clk(void)
157 struct s5pc110_clock *clk =
158 (struct s5pc110_clock *)samsung_get_base_clock();
160 unsigned long dout_apll, armclk;
161 unsigned int apll_ratio;
163 div = readl(&clk->div0);
165 /* APLL_RATIO: [2:0] */
166 apll_ratio = div & 0x7;
168 dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
174 /* s5pc100: return ARM clock frequency */
175 static unsigned long s5pc100_get_arm_clk(void)
177 struct s5pc100_clock *clk =
178 (struct s5pc100_clock *)samsung_get_base_clock();
180 unsigned long dout_apll, armclk;
181 unsigned int apll_ratio, arm_ratio;
183 div = readl(&clk->div0);
185 /* ARM_RATIO: [6:4] */
186 arm_ratio = (div >> 4) & 0x7;
187 /* APLL_RATIO: [0] */
188 apll_ratio = div & 0x1;
190 dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
191 armclk = dout_apll / (arm_ratio + 1);
196 /* s5pc100: return HCLKD0 frequency */
197 static unsigned long get_hclk(void)
199 struct s5pc100_clock *clk =
200 (struct s5pc100_clock *)samsung_get_base_clock();
201 unsigned long hclkd0;
202 uint div, d0_bus_ratio;
204 div = readl(&clk->div0);
205 /* D0_BUS_RATIO: [10:8] */
206 d0_bus_ratio = (div >> 8) & 0x7;
208 hclkd0 = get_arm_clk() / (d0_bus_ratio + 1);
213 /* s5pc100: return PCLKD1 frequency */
214 static unsigned long get_pclkd1(void)
216 struct s5pc100_clock *clk =
217 (struct s5pc100_clock *)samsung_get_base_clock();
218 unsigned long d1_bus, pclkd1;
219 uint div, d1_bus_ratio, pclkd1_ratio;
221 div = readl(&clk->div0);
222 /* D1_BUS_RATIO: [14:12] */
223 d1_bus_ratio = (div >> 12) & 0x7;
224 /* PCLKD1_RATIO: [18:16] */
225 pclkd1_ratio = (div >> 16) & 0x7;
228 d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1);
229 pclkd1 = d1_bus / (pclkd1_ratio + 1);
234 /* s5pc110: return HCLKs frequency */
235 static unsigned long get_hclk_sys(int dom)
237 struct s5pc110_clock *clk =
238 (struct s5pc110_clock *)samsung_get_base_clock();
242 unsigned int hclk_sys_ratio;
247 div = readl(&clk->div0);
250 * HCLK_MSYS_RATIO: [10:8]
251 * HCLK_DSYS_RATIO: [19:16]
252 * HCLK_PSYS_RATIO: [27:24]
254 offset = 8 + (dom << 0x3);
256 hclk_sys_ratio = (div >> offset) & 0xf;
258 hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1);
263 /* s5pc110: return PCLKs frequency */
264 static unsigned long get_pclk_sys(int dom)
266 struct s5pc110_clock *clk =
267 (struct s5pc110_clock *)samsung_get_base_clock();
271 unsigned int pclk_sys_ratio;
273 div = readl(&clk->div0);
276 * PCLK_MSYS_RATIO: [14:12]
277 * PCLK_DSYS_RATIO: [22:20]
278 * PCLK_PSYS_RATIO: [30:28]
280 offset = 12 + (dom << 0x3);
282 pclk_sys_ratio = (div >> offset) & 0x7;
284 pclk = get_hclk_sys(dom) / (pclk_sys_ratio + 1);
289 /* s5pc110: return peripheral clock frequency */
290 static unsigned long s5pc110_get_pclk(void)
292 return get_pclk_sys(CLK_P);
295 /* s5pc100: return peripheral clock frequency */
296 static unsigned long s5pc100_get_pclk(void)
301 /* s5pc1xx: return uart clock frequency */
302 static unsigned long s5pc1xx_get_uart_clk(int dev_index)
304 if (cpu_is_s5pc110())
305 return s5pc110_get_pclk();
307 return s5pc100_get_pclk();
310 /* s5pc1xx: return pwm clock frequency */
311 static unsigned long s5pc1xx_get_pwm_clk(void)
313 if (cpu_is_s5pc110())
314 return s5pc110_get_pclk();
316 return s5pc100_get_pclk();
319 void s5p_clock_init(void)
321 if (cpu_is_s5pc110()) {
322 get_pll_clk = s5pc110_get_pll_clk;
323 get_arm_clk = s5pc110_get_arm_clk;
325 get_pll_clk = s5pc100_get_pll_clk;
326 get_arm_clk = s5pc100_get_arm_clk;
328 get_uart_clk = s5pc1xx_get_uart_clk;
329 get_pwm_clk = s5pc1xx_get_pwm_clk;