arch/arm/cpu/armv7/omap5/sdram.c

   1 /*
   2  * Timing and Organization details of the ddr device parts used in OMAP5
   3  * EVM
   4  *
   5  * (C) Copyright 2010
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Aneesh V <aneesh@ti.com>
   9  * Sricharan R <r.sricharan@ti.com>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #include <asm/emif.h>
  15 #include <asm/arch/sys_proto.h>
  16
  17 /*
  18  * This file provides details of the LPDDR2 SDRAM parts used on OMAP5
  19  * EVM. Since the parts used and geometry are identical for
  20  * evm for a given OMAP5 revision, this information is kept
  21  * here instead of being in board directory. However the key functions
  22  * exported are weakly linked so that they can be over-ridden in the board
  23  * directory if there is a OMAP5 board in the future that uses a different
  24  * memory device or geometry.
  25  *
  26  * For any new board with different memory devices over-ride one or more
  27  * of the following functions as per the CONFIG flags you intend to enable:
  28  * - emif_get_reg_dump()
  29  * - emif_get_dmm_regs()
  30  * - emif_get_device_details()
  31  * - emif_get_device_timings()
  32  */
  33
  34 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  35 const struct emif_regs emif_regs_532_mhz_2cs = {
  36         .sdram_config_init              = 0x80800EBA,
  37         .sdram_config                   = 0x808022BA,
  38         .ref_ctrl                       = 0x0000081A,
  39         .sdram_tim1                     = 0x772F6873,
  40         .sdram_tim2                     = 0x304a129a,
  41         .sdram_tim3                     = 0x02f7e45f,
  42         .read_idle_ctrl                 = 0x00050000,
  43         .zq_config                      = 0x000b3215,
  44         .temp_alert_config              = 0x08000a05,
  45         .emif_ddr_phy_ctlr_1_init       = 0x0E28420d,
  46         .emif_ddr_phy_ctlr_1            = 0x0E28420d,
  47         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  48         .emif_ddr_ext_phy_ctrl_2        = 0x28C518A3,
  49         .emif_ddr_ext_phy_ctrl_3        = 0x518A3146,
  50         .emif_ddr_ext_phy_ctrl_4        = 0x0014628C,
  51         .emif_ddr_ext_phy_ctrl_5        = 0x04010040
  52 };
  53
  54 const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
  55         .sdram_config_init              = 0x80800EBA,
  56         .sdram_config                   = 0x808022BA,
  57         .ref_ctrl                       = 0x0000081A,
  58         .sdram_tim1                     = 0x772F6873,
  59         .sdram_tim2                     = 0x304a129a,
  60         .sdram_tim3                     = 0x02f7e45f,
  61         .read_idle_ctrl                 = 0x00050000,
  62         .zq_config                      = 0x100b3215,
  63         .temp_alert_config              = 0x08000a05,
  64         .emif_ddr_phy_ctlr_1_init       = 0x0E30400d,
  65         .emif_ddr_phy_ctlr_1            = 0x0E30400d,
  66         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  67         .emif_ddr_ext_phy_ctrl_2        = 0x28C518A3,
  68         .emif_ddr_ext_phy_ctrl_3        = 0x518A3146,
  69         .emif_ddr_ext_phy_ctrl_4        = 0x0014628C,
  70         .emif_ddr_ext_phy_ctrl_5        = 0xC330CC33,
  71 };
  72
  73 const struct emif_regs emif_regs_266_mhz_2cs = {
  74         .sdram_config_init              = 0x80800EBA,
  75         .sdram_config                   = 0x808022BA,
  76         .ref_ctrl                       = 0x0000040D,
  77         .sdram_tim1                     = 0x2A86B419,
  78         .sdram_tim2                     = 0x1025094A,
  79         .sdram_tim3                     = 0x026BA22F,
  80         .read_idle_ctrl                 = 0x00050000,
  81         .zq_config                      = 0x000b3215,
  82         .temp_alert_config              = 0x08000a05,
  83         .emif_ddr_phy_ctlr_1_init       = 0x0E28420d,
  84         .emif_ddr_phy_ctlr_1            = 0x0E28420d,
  85         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  86         .emif_ddr_ext_phy_ctrl_2        = 0x0A414829,
  87         .emif_ddr_ext_phy_ctrl_3        = 0x14829052,
  88         .emif_ddr_ext_phy_ctrl_4        = 0x000520A4,
  89         .emif_ddr_ext_phy_ctrl_5        = 0x04010040
  90 };
  91
  92 const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
  93         .sdram_config_init              = 0x61851B32,
  94         .sdram_config                   = 0x61851B32,
  95         .sdram_config2                  = 0x0,
  96         .ref_ctrl                       = 0x00001035,
  97         .sdram_tim1                     = 0xCCCF36B3,
  98         .sdram_tim2                     = 0x308F7FDA,
  99         .sdram_tim3                     = 0x027F88A8,
 100         .read_idle_ctrl                 = 0x00050000,
 101         .zq_config                      = 0x0007190B,
 102         .temp_alert_config              = 0x00000000,
 103         .emif_ddr_phy_ctlr_1_init       = 0x0020420A,
 104         .emif_ddr_phy_ctlr_1            = 0x0024420A,
 105         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 106         .emif_ddr_ext_phy_ctrl_2        = 0x00000000,
 107         .emif_ddr_ext_phy_ctrl_3        = 0x00000000,
 108         .emif_ddr_ext_phy_ctrl_4        = 0x00000000,
 109         .emif_ddr_ext_phy_ctrl_5        = 0x04010040,
 110         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 111         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 112         .emif_rd_wr_lvl_ctl             = 0x00000000,
 113         .emif_rd_wr_exec_thresh         = 0x00000305
 114 };
 115
 116 const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
 117         .sdram_config_init              = 0x61851B32,
 118         .sdram_config                   = 0x61851B32,
 119         .sdram_config2                  = 0x0,
 120         .ref_ctrl                       = 0x00001035,
 121         .sdram_tim1                     = 0xCCCF36B3,
 122         .sdram_tim2                     = 0x308F7FDA,
 123         .sdram_tim3                     = 0x027F88A8,
 124         .read_idle_ctrl                 = 0x00050000,
 125         .zq_config                      = 0x1007190B,
 126         .temp_alert_config              = 0x00000000,
 127         .emif_ddr_phy_ctlr_1_init       = 0x0030400A,
 128         .emif_ddr_phy_ctlr_1            = 0x0034400A,
 129         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 130         .emif_ddr_ext_phy_ctrl_2        = 0x00000000,
 131         .emif_ddr_ext_phy_ctrl_3        = 0x00000000,
 132         .emif_ddr_ext_phy_ctrl_4        = 0x00000000,
 133         .emif_ddr_ext_phy_ctrl_5        = 0x4350D435,
 134         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 135         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 136         .emif_rd_wr_lvl_ctl             = 0x00000000,
 137         .emif_rd_wr_exec_thresh         = 0x40000305
 138 };
 139
 140 const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
 141         .dmm_lisa_map_0 = 0x0,
 142         .dmm_lisa_map_1 = 0x0,
 143         .dmm_lisa_map_2 = 0x80740300,
 144         .dmm_lisa_map_3 = 0xFF020100,
 145         .is_ma_present  = 0x1
 146 };
 147
 148 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 149 {
 150         switch (omap_revision()) {
 151         case OMAP5430_ES1_0:
 152                 *regs = &emif_regs_532_mhz_2cs;
 153                 break;
 154         case OMAP5432_ES1_0:
 155                 *regs = &emif_regs_ddr3_532_mhz_1cs;
 156                 break;
 157         case OMAP5430_ES2_0:
 158                 *regs = &emif_regs_532_mhz_2cs_es2;
 159                 break;
 160         case OMAP5432_ES2_0:
 161         default:
 162                 *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
 163                 break;
 164         }
 165 }
 166
 167 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 168         __attribute__((weak, alias("emif_get_reg_dump_sdp")));
 169
 170 static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 171                                                 **dmm_lisa_regs)
 172 {
 173         switch (omap_revision()) {
 174         case OMAP5430_ES1_0:
 175         case OMAP5430_ES2_0:
 176         case OMAP5432_ES1_0:
 177         case OMAP5432_ES2_0:
 178         default:
 179                 *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
 180                 break;
 181         }
 182
 183 }
 184
 185 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 186         __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
 187 #else
 188
 189 static const struct lpddr2_device_details dev_4G_S4_details = {
 190         .type           = LPDDR2_TYPE_S4,
 191         .density        = LPDDR2_DENSITY_4Gb,
 192         .io_width       = LPDDR2_IO_WIDTH_32,
 193         .manufacturer   = LPDDR2_MANUFACTURER_SAMSUNG
 194 };
 195
 196 static void emif_get_device_details_sdp(u32 emif_nr,
 197                 struct lpddr2_device_details *cs0_device_details,
 198                 struct lpddr2_device_details *cs1_device_details)
 199 {
 200         /* EMIF1 & EMIF2 have identical configuration */
 201         *cs0_device_details = dev_4G_S4_details;
 202         *cs1_device_details = dev_4G_S4_details;
 203 }
 204
 205 void emif_get_device_details(u32 emif_nr,
 206                 struct lpddr2_device_details *cs0_device_details,
 207                 struct lpddr2_device_details *cs1_device_details)
 208         __attribute__((weak, alias("emif_get_device_details_sdp")));
 209
 210 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 211
 212 const u32 ext_phy_ctrl_const_base[] = {
 213         0x01004010,
 214         0x00001004,
 215         0x04010040,
 216         0x01004010,
 217         0x00001004,
 218         0x00000000,
 219         0x00000000,
 220         0x00000000,
 221         0x80080080,
 222         0x00800800,
 223         0x08102040,
 224         0x00000001,
 225         0x540A8150,
 226         0xA81502a0,
 227         0x002A0540,
 228         0x00000000,
 229         0x00000000,
 230         0x00000000,
 231         0x00000077,
 232         0x0
 233 };
 234
 235 const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
 236         0x01004010,
 237         0x00001004,
 238         0x04010040,
 239         0x01004010,
 240         0x00001004,
 241         0x00000000,
 242         0x00000000,
 243         0x00000000,
 244         0x80080080,
 245         0x00800800,
 246         0x08102040,
 247         0x00000002,
 248         0x0,
 249         0x0,
 250         0x0,
 251         0x00000000,
 252         0x00000000,
 253         0x00000000,
 254         0x00000057,
 255         0x0
 256 };
 257
 258 const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
 259         0x50D4350D,
 260         0x00000D43,
 261         0x04010040,
 262         0x01004010,
 263         0x00001004,
 264         0x00000000,
 265         0x00000000,
 266         0x00000000,
 267         0x80080080,
 268         0x00800800,
 269         0x08102040,
 270         0x00000002,
 271         0x00000000,
 272         0x00000000,
 273         0x00000000,
 274         0x00000000,
 275         0x00000000,
 276         0x00000000,
 277         0x00000057,
 278         0x0
 279 };
 280
 281 /* Ext phy ctrl 1-35 regs */
 282 const u32
 283 dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
 284         0x10040100,
 285         0x00910091,
 286         0x00950095,
 287         0x009B009B,
 288         0x009E009E,
 289         0x00980098,
 290         0x00340034,
 291         0x00350035,
 292         0x00340034,
 293         0x00310031,
 294         0x00340034,
 295         0x007F007F,
 296         0x007F007F,
 297         0x007F007F,
 298         0x007F007F,
 299         0x007F007F,
 300         0x00480048,
 301         0x004A004A,
 302         0x00520052,
 303         0x00550055,
 304         0x00500050,
 305         0x00000000,
 306         0x00600020,
 307         0x40011080,
 308         0x08102040,
 309         0x0,
 310         0x0,
 311         0x0,
 312         0x0,
 313         0x0,
 314         0x0,
 315         0x0,
 316         0x0,
 317         0x0,
 318         0x0
 319 };
 320
 321 /* Ext phy ctrl 1-35 regs */
 322 const u32
 323 dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
 324         0x10040100,
 325         0x00910091,
 326         0x00950095,
 327         0x009B009B,
 328         0x009E009E,
 329         0x00980098,
 330         0x00330033,
 331         0x00330033,
 332         0x002F002F,
 333         0x00320032,
 334         0x00310031,
 335         0x007F007F,
 336         0x007F007F,
 337         0x007F007F,
 338         0x007F007F,
 339         0x007F007F,
 340         0x00520052,
 341         0x00520052,
 342         0x00470047,
 343         0x00490049,
 344         0x00500050,
 345         0x00000000,
 346         0x00600020,
 347         0x40011080,
 348         0x08102040,
 349         0x0,
 350         0x0,
 351         0x0,
 352         0x0,
 353         0x0,
 354         0x0,
 355         0x0,
 356         0x0,
 357         0x0,
 358         0x0
 359 };
 360
 361 /* Ext phy ctrl 1-35 regs */
 362 const u32
 363 dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
 364         0x10040100,
 365         0x00A400A4,
 366         0x00A900A9,
 367         0x00B000B0,
 368         0x00B000B0,
 369         0x00A400A4,
 370         0x00390039,
 371         0x00320032,
 372         0x00320032,
 373         0x00320032,
 374         0x00440044,
 375         0x00550055,
 376         0x00550055,
 377         0x00550055,
 378         0x00550055,
 379         0x007F007F,
 380         0x004D004D,
 381         0x00430043,
 382         0x00560056,
 383         0x00540054,
 384         0x00600060,
 385         0x0,
 386         0x00600020,
 387         0x40010080,
 388         0x08102040,
 389         0x0,
 390         0x0,
 391         0x0,
 392         0x0,
 393         0x0,
 394         0x0,
 395         0x0,
 396         0x0,
 397         0x0,
 398         0x0
 399 };
 400
 401 const struct lpddr2_mr_regs mr_regs = {
 402         .mr1    = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
 403         .mr2    = 0x6,
 404         .mr3    = 0x1,
 405         .mr10   = MR10_ZQ_ZQINIT,
 406         .mr16   = MR16_REF_FULL_ARRAY
 407 };
 408
 409 void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
 410                                              const u32 **regs,
 411                                              u32 *size)
 412 {
 413         switch (omap_revision()) {
 414         case OMAP5430_ES1_0:
 415         case OMAP5430_ES2_0:
 416                 *regs = ext_phy_ctrl_const_base;
 417                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base);
 418                 break;
 419         case OMAP5432_ES1_0:
 420                 *regs = ddr3_ext_phy_ctrl_const_base_es1;
 421                 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
 422                 break;
 423         case OMAP5432_ES2_0:
 424                 *regs = ddr3_ext_phy_ctrl_const_base_es2;
 425                 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
 426                 break;
 427         case DRA752_ES1_0:
 428         case DRA752_ES1_1:
 429         case DRA752_ES2_0:
 430                 if (emif_nr == 1) {
 431                         *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
 432                         *size =
 433                         ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
 434                 } else {
 435                         *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
 436                         *size =
 437                         ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
 438                 }
 439                 break;
 440         case DRA722_ES1_0:
 441         case DRA722_ES2_0:
 442                 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
 443                 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
 444                 break;
 445         default:
 446                 *regs = ddr3_ext_phy_ctrl_const_base_es2;
 447                 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
 448
 449         }
 450 }
 451
 452 void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
 453 {
 454         *regs = &mr_regs;
 455 }
 456
 457 static void do_ext_phy_settings_omap5(u32 base, const struct emif_regs *regs)
 458 {
 459         u32 *ext_phy_ctrl_base = 0;
 460         u32 *emif_ext_phy_ctrl_base = 0;
 461         u32 emif_nr;
 462         const u32 *ext_phy_ctrl_const_regs;
 463         u32 i = 0;
 464         u32 size;
 465
 466         emif_nr = (base == EMIF1_BASE) ? 1 : 2;
 467
 468         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 469
 470         ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
 471         emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
 472
 473         /* Configure external phy control timing registers */
 474         for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
 475                 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
 476                 /* Update shadow registers */
 477                 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
 478         }
 479
 480         /*
 481          * external phy 6-24 registers do not change with
 482          * ddr frequency
 483          */
 484         emif_get_ext_phy_ctrl_const_regs(emif_nr,
 485                                          &ext_phy_ctrl_const_regs, &size);
 486
 487         for (i = 0; i < size; i++) {
 488                 writel(ext_phy_ctrl_const_regs[i],
 489                        emif_ext_phy_ctrl_base++);
 490                 /* Update shadow registers */
 491                 writel(ext_phy_ctrl_const_regs[i],
 492                        emif_ext_phy_ctrl_base++);
 493         }
 494 }
 495
 496 static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs)
 497 {
 498         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 499         u32 *emif_ext_phy_ctrl_base = 0;
 500         u32 emif_nr;
 501         const u32 *ext_phy_ctrl_const_regs;
 502         u32 i, hw_leveling, size, phy;
 503
 504         emif_nr = (base == EMIF1_BASE) ? 1 : 2;
 505
 506         hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT;
 507         phy = regs->emif_ddr_phy_ctlr_1_init;
 508
 509         emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1);
 510
 511         emif_get_ext_phy_ctrl_const_regs(emif_nr,
 512                                          &ext_phy_ctrl_const_regs, &size);
 513
 514         writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]);
 515         writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]);
 516
 517         /*
 518          * Copy the predefined PHY register values
 519          * if leveling is disabled.
 520          */
 521         if (phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)
 522                 for (i = 1; i < 6; i++) {
 523                         writel(ext_phy_ctrl_const_regs[i],
 524                                &emif_ext_phy_ctrl_base[i * 2]);
 525                         writel(ext_phy_ctrl_const_regs[i],
 526                                &emif_ext_phy_ctrl_base[i * 2 + 1]);
 527                 }
 528
 529         if (phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK)
 530                 for (i = 6; i < 11; i++) {
 531                         writel(ext_phy_ctrl_const_regs[i],
 532                                &emif_ext_phy_ctrl_base[i * 2]);
 533                         writel(ext_phy_ctrl_const_regs[i],
 534                                &emif_ext_phy_ctrl_base[i * 2 + 1]);
 535                 }
 536
 537         if (phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)
 538                 for (i = 11; i < 25; i++) {
 539                         writel(ext_phy_ctrl_const_regs[i],
 540                                &emif_ext_phy_ctrl_base[i * 2]);
 541                         writel(ext_phy_ctrl_const_regs[i],
 542                                &emif_ext_phy_ctrl_base[i * 2 + 1]);
 543                 }
 544
 545         if (hw_leveling) {
 546                 /*
 547                  * Write the init value for HW levling to occur
 548                  */
 549                 for (i = 21; i < 35; i++) {
 550                         writel(ext_phy_ctrl_const_regs[i],
 551                                &emif_ext_phy_ctrl_base[i * 2]);
 552                         writel(ext_phy_ctrl_const_regs[i],
 553                                &emif_ext_phy_ctrl_base[i * 2 + 1]);
 554                 }
 555         }
 556 }
 557
 558 void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 559 {
 560         if (is_omap54xx())
 561                 do_ext_phy_settings_omap5(base, regs);
 562         else
 563                 do_ext_phy_settings_dra7(base, regs);
 564 }
 565
 566 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 567 static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
 568         .max_freq       = 532000000,
 569         .RL             = 8,
 570         .tRPab          = 21,
 571         .tRCD           = 18,
 572         .tWR            = 15,
 573         .tRASmin        = 42,
 574         .tRRD           = 10,
 575         .tWTRx2         = 15,
 576         .tXSR           = 140,
 577         .tXPx2          = 15,
 578         .tRFCab         = 130,
 579         .tRTPx2         = 15,
 580         .tCKE           = 3,
 581         .tCKESR         = 15,
 582         .tZQCS          = 90,
 583         .tZQCL          = 360,
 584         .tZQINIT        = 1000,
 585         .tDQSCKMAXx2    = 11,
 586         .tRASmax        = 70,
 587         .tFAW           = 50
 588 };
 589
 590 static const struct lpddr2_min_tck min_tck = {
 591         .tRL            = 3,
 592         .tRP_AB         = 3,
 593         .tRCD           = 3,
 594         .tWR            = 3,
 595         .tRAS_MIN       = 3,
 596         .tRRD           = 2,
 597         .tWTR           = 2,
 598         .tXP            = 2,
 599         .tRTP           = 2,
 600         .tCKE           = 3,
 601         .tCKESR         = 3,
 602         .tFAW           = 8
 603 };
 604
 605 static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
 606         &timings_jedec_532_mhz
 607 };
 608
 609 static const struct lpddr2_device_timings dev_4G_S4_timings = {
 610         .ac_timings     = ac_timings,
 611         .min_tck        = &min_tck,
 612 };
 613
 614 /*
 615  * List of status registers to be controlled back to control registers
 616  * after initial leveling
 617  * readreg, writereg
 618  */
 619 const struct read_write_regs omap5_bug_00339_regs[] = {
 620         { 8,  5 },
 621         { 9,  6 },
 622         { 10, 7 },
 623         { 14, 8 },
 624         { 15, 9 },
 625         { 16, 10 },
 626         { 11, 2 },
 627         { 12, 3 },
 628         { 13, 4 },
 629         { 17, 11 },
 630         { 18, 12 },
 631         { 19, 13 },
 632 };
 633
 634 const struct read_write_regs dra_bug_00339_regs[] = {
 635         { 7,  7 },
 636         { 8,  8 },
 637         { 9,  9 },
 638         { 10, 10 },
 639         { 11, 11 },
 640         { 12, 2 },
 641         { 13, 3 },
 642         { 14, 4 },
 643         { 15, 5 },
 644         { 16, 6 },
 645         { 17, 12 },
 646         { 18, 13 },
 647         { 19, 14 },
 648         { 20, 15 },
 649         { 21, 16 },
 650         { 22, 17 },
 651         { 23, 18 },
 652         { 24, 19 },
 653         { 25, 20 },
 654         { 26, 21}
 655 };
 656
 657 const struct read_write_regs *get_bug_regs(u32 *iterations)
 658 {
 659         const struct read_write_regs *bug_00339_regs_ptr = NULL;
 660
 661         switch (omap_revision()) {
 662         case OMAP5430_ES1_0:
 663         case OMAP5430_ES2_0:
 664         case OMAP5432_ES1_0:
 665         case OMAP5432_ES2_0:
 666                 bug_00339_regs_ptr = omap5_bug_00339_regs;
 667                 *iterations = sizeof(omap5_bug_00339_regs)/
 668                              sizeof(omap5_bug_00339_regs[0]);
 669                 break;
 670         case DRA752_ES1_0:
 671         case DRA752_ES1_1:
 672         case DRA752_ES2_0:
 673         case DRA722_ES1_0:
 674         case DRA722_ES2_0:
 675                 bug_00339_regs_ptr = dra_bug_00339_regs;
 676                 *iterations = sizeof(dra_bug_00339_regs)/
 677                              sizeof(dra_bug_00339_regs[0]);
 678                 break;
 679         default:
 680                 printf("\n Error: UnKnown SOC");
 681         }
 682
 683         return bug_00339_regs_ptr;
 684 }
 685
 686 void emif_get_device_timings_sdp(u32 emif_nr,
 687                 const struct lpddr2_device_timings **cs0_device_timings,
 688                 const struct lpddr2_device_timings **cs1_device_timings)
 689 {
 690         /* Identical devices on EMIF1 & EMIF2 */
 691         *cs0_device_timings = &dev_4G_S4_timings;
 692         *cs1_device_timings = &dev_4G_S4_timings;
 693 }
 694
 695 void emif_get_device_timings(u32 emif_nr,
 696                 const struct lpddr2_device_timings **cs0_device_timings,
 697                 const struct lpddr2_device_timings **cs1_device_timings)
 698         __attribute__((weak, alias("emif_get_device_timings_sdp")));
 699
 700 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */