3 * Functions for omap5 based boards.
6 * Texas Instruments, <www.ti.com>
9 * Aneesh V <aneesh@ti.com>
10 * Steve Sakoman <steve@sakoman.com>
11 * Sricharan <r.sricharan@ti.com>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm/armv7.h>
33 #include <asm/arch/cpu.h>
34 #include <asm/arch/sys_proto.h>
35 #include <asm/arch/clocks.h>
36 #include <asm/sizes.h>
37 #include <asm/utils.h>
38 #include <asm/arch/gpio.h>
41 DECLARE_GLOBAL_DATA_PTR;
43 u32 *const omap_si_rev = (u32 *)OMAP5_SRAM_SCRATCH_OMAP5_REV;
45 static struct gpio_bank gpio_bank_54xx[6] = {
46 { (void *)OMAP54XX_GPIO1_BASE, METHOD_GPIO_24XX },
47 { (void *)OMAP54XX_GPIO2_BASE, METHOD_GPIO_24XX },
48 { (void *)OMAP54XX_GPIO3_BASE, METHOD_GPIO_24XX },
49 { (void *)OMAP54XX_GPIO4_BASE, METHOD_GPIO_24XX },
50 { (void *)OMAP54XX_GPIO5_BASE, METHOD_GPIO_24XX },
51 { (void *)OMAP54XX_GPIO6_BASE, METHOD_GPIO_24XX },
54 const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
56 #ifdef CONFIG_SPL_BUILD
57 /* LPDDR2 specific IO settings */
58 static void io_settings_lpddr2(void)
60 const struct ctrl_ioregs *ioregs;
63 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
64 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
65 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
66 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
67 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
68 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
69 writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
70 writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
71 writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
74 /* DDR3 specific IO settings */
75 static void io_settings_ddr3(void)
78 const struct ctrl_ioregs *ioregs;
81 writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch1_0);
82 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
83 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
85 writel(ioregs->ctrl_ddr3ch, (*ctrl)->control_ddr3ch2_0);
86 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
87 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
89 writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
90 writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
91 writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
93 /* omap5432 does not use lpddr2 */
94 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
95 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
97 writel(ioregs->ctrl_emif_sdram_config_ext,
98 (*ctrl)->control_emif1_sdram_config_ext);
99 writel(ioregs->ctrl_emif_sdram_config_ext,
100 (*ctrl)->control_emif2_sdram_config_ext);
102 /* Disable DLL select */
103 io_settings = (readl((*ctrl)->control_port_emif1_sdram_config)
106 (*ctrl)->control_port_emif1_sdram_config);
108 io_settings = (readl((*ctrl)->control_port_emif2_sdram_config)
111 (*ctrl)->control_port_emif2_sdram_config);
115 * Some tuning of IOs for optimal power and performance
117 void do_io_settings(void)
119 u32 io_settings = 0, mask = 0;
121 /* Impedance settings EMMC, C2C 1,2, hsi2 */
122 mask = (ds_mask << 2) | (ds_mask << 8) |
123 (ds_mask << 16) | (ds_mask << 18);
124 io_settings = readl((*ctrl)->control_smart1io_padconf_0) &
126 io_settings |= (ds_60_ohm << 8) | (ds_45_ohm << 16) |
127 (ds_45_ohm << 18) | (ds_60_ohm << 2);
128 writel(io_settings, (*ctrl)->control_smart1io_padconf_0);
130 /* Impedance settings Mcspi2 */
131 mask = (ds_mask << 30);
132 io_settings = readl((*ctrl)->control_smart1io_padconf_1) &
134 io_settings |= (ds_60_ohm << 30);
135 writel(io_settings, (*ctrl)->control_smart1io_padconf_1);
137 /* Impedance settings C2C 3,4 */
138 mask = (ds_mask << 14) | (ds_mask << 16);
139 io_settings = readl((*ctrl)->control_smart1io_padconf_2) &
141 io_settings |= (ds_45_ohm << 14) | (ds_45_ohm << 16);
142 writel(io_settings, (*ctrl)->control_smart1io_padconf_2);
144 /* Slew rate settings EMMC, C2C 1,2 */
145 mask = (sc_mask << 8) | (sc_mask << 16) | (sc_mask << 18);
146 io_settings = readl((*ctrl)->control_smart2io_padconf_0) &
148 io_settings |= (sc_fast << 8) | (sc_na << 16) | (sc_na << 18);
149 writel(io_settings, (*ctrl)->control_smart2io_padconf_0);
151 /* Slew rate settings hsi2, Mcspi2 */
152 mask = (sc_mask << 24) | (sc_mask << 28);
153 io_settings = readl((*ctrl)->control_smart2io_padconf_1) &
155 io_settings |= (sc_fast << 28) | (sc_fast << 24);
156 writel(io_settings, (*ctrl)->control_smart2io_padconf_1);
158 /* Slew rate settings C2C 3,4 */
159 mask = (sc_mask << 16) | (sc_mask << 18);
160 io_settings = readl((*ctrl)->control_smart2io_padconf_2) &
162 io_settings |= (sc_na << 16) | (sc_na << 18);
163 writel(io_settings, (*ctrl)->control_smart2io_padconf_2);
165 /* impedance and slew rate settings for usb */
166 mask = (usb_i_mask << 29) | (usb_i_mask << 26) | (usb_i_mask << 23) |
167 (usb_i_mask << 20) | (usb_i_mask << 17) | (usb_i_mask << 14);
168 io_settings = readl((*ctrl)->control_smart3io_padconf_1) &
170 io_settings |= (ds_60_ohm << 29) | (ds_60_ohm << 26) |
171 (ds_60_ohm << 23) | (sc_fast << 20) |
172 (sc_fast << 17) | (sc_fast << 14);
173 writel(io_settings, (*ctrl)->control_smart3io_padconf_1);
175 if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
176 io_settings_lpddr2();
181 writel(EFUSE_1, (*ctrl)->control_efuse_1);
182 writel(EFUSE_2, (*ctrl)->control_efuse_2);
183 writel(EFUSE_3, (*ctrl)->control_efuse_3);
184 writel(EFUSE_4, (*ctrl)->control_efuse_4);
187 static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
188 {0x45, 0x1}, /* 12 MHz */
189 {-1, -1}, /* 13 MHz */
190 {0x63, 0x2}, /* 16.8 MHz */
191 {0x57, 0x2}, /* 19.2 MHz */
192 {0x20, 0x1}, /* 26 MHz */
193 {-1, -1}, /* 27 MHz */
194 {0x41, 0x3} /* 38.4 MHz */
197 void srcomp_enable(void)
199 u32 srcomp_value, mul_factor, div_factor, clk_val, i;
200 u32 sysclk_ind = get_sys_clk_index();
201 u32 omap_rev = omap_revision();
203 mul_factor = srcomp_parameters[sysclk_ind].multiply_factor;
204 div_factor = srcomp_parameters[sysclk_ind].divide_factor;
206 for (i = 0; i < 4; i++) {
207 srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4);
209 ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK);
210 srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
211 (div_factor << DIVIDE_FACTOR_XS_SHIFT);
212 writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4);
215 if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) {
216 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
217 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
218 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
220 for (i = 0; i < 4; i++) {
222 readl((*ctrl)->control_srcomp_north_side + i*4);
223 srcomp_value &= ~PWRDWN_XS_MASK;
225 (*ctrl)->control_srcomp_north_side + i*4);
227 while (((readl((*ctrl)->control_srcomp_north_side + i*4)
228 & SRCODE_READ_XS_MASK) >>
229 SRCODE_READ_XS_SHIFT) == 0)
233 readl((*ctrl)->control_srcomp_north_side + i*4);
234 srcomp_value &= ~OVERRIDE_XS_MASK;
236 (*ctrl)->control_srcomp_north_side + i*4);
239 srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup);
240 srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK |
241 DIVIDE_FACTOR_XS_MASK);
242 srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) |
243 (div_factor << DIVIDE_FACTOR_XS_SHIFT);
244 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
246 for (i = 0; i < 4; i++) {
248 readl((*ctrl)->control_srcomp_north_side + i*4);
249 srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
251 (*ctrl)->control_srcomp_north_side + i*4);
254 readl((*ctrl)->control_srcomp_north_side + i*4);
255 srcomp_value &= ~OVERRIDE_XS_MASK;
257 (*ctrl)->control_srcomp_north_side + i*4);
261 readl((*ctrl)->control_srcomp_east_side_wkup);
262 srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK;
263 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
266 readl((*ctrl)->control_srcomp_east_side_wkup);
267 srcomp_value &= ~OVERRIDE_XS_MASK;
268 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
270 clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl);
271 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
272 writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl);
274 clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl);
275 clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK;
276 writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl);
278 for (i = 0; i < 4; i++) {
279 while (((readl((*ctrl)->control_srcomp_north_side + i*4)
280 & SRCODE_READ_XS_MASK) >>
281 SRCODE_READ_XS_SHIFT) == 0)
285 readl((*ctrl)->control_srcomp_north_side + i*4);
286 srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
288 (*ctrl)->control_srcomp_north_side + i*4);
291 while (((readl((*ctrl)->control_srcomp_east_side_wkup) &
292 SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0)
296 readl((*ctrl)->control_srcomp_east_side_wkup);
297 srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK;
298 writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup);
303 void config_data_eye_leveling_samples(u32 emif_base)
305 /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
306 if (emif_base == EMIF1_BASE)
307 writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
308 (*ctrl)->control_emif1_sdram_config_ext);
309 else if (emif_base == EMIF2_BASE)
310 writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
311 (*ctrl)->control_emif2_sdram_config_ext);
314 void init_omap_revision(void)
317 * For some of the ES2/ES1 boards ID_CODE is not reliable:
318 * Also, ES1 and ES2 have different ARM revisions
319 * So use ARM revision for identification
321 unsigned int rev = cortex_rev();
323 switch (readl(CONTROL_ID_CODE)) {
324 case OMAP5430_CONTROL_ID_CODE_ES1_0:
325 *omap_si_rev = OMAP5430_ES1_0;
326 if (rev == MIDR_CORTEX_A15_R2P2)
327 *omap_si_rev = OMAP5430_ES2_0;
329 case OMAP5432_CONTROL_ID_CODE_ES1_0:
330 *omap_si_rev = OMAP5432_ES1_0;
331 if (rev == MIDR_CORTEX_A15_R2P2)
332 *omap_si_rev = OMAP5432_ES2_0;
334 case OMAP5430_CONTROL_ID_CODE_ES2_0:
335 *omap_si_rev = OMAP5430_ES2_0;
337 case OMAP5432_CONTROL_ID_CODE_ES2_0:
338 *omap_si_rev = OMAP5432_ES2_0;
341 *omap_si_rev = OMAP5430_SILICON_ID_INVALID;
345 void reset_cpu(ulong ignored)
347 u32 omap_rev = omap_revision();
350 * WARM reset is not functional in case of OMAP5430 ES1.0 soc.
351 * So use cold reset in case instead.
353 if (omap_rev == OMAP5430_ES1_0)
354 writel(PRM_RSTCTRL_RESET << 0x1, (*prcm)->prm_rstctrl);
356 writel(PRM_RSTCTRL_RESET, (*prcm)->prm_rstctrl);
361 return readl((*prcm)->prm_rstst) & PRM_RSTST_WARM_RESET_MASK;